CSE477VLSI Digital CircuitsFall 2003 Lecture 07: Pass Transistor LogicReview: Static Complementary CMOSReview: Static CMOS Full Adder CircuitNMOS Transistors in Series/ParallelPMOS Transistors in Series/ParallelPass Transistor (PT) LogicPass Transistor (PT) LogicVTC of PT AND GateDifferential PT Logic (CPL)CPL PropertiesCPL Full AdderCPL Full AdderNMOS Only PT Driving an InverterVoltage Swing of PT Driving an InverterCascaded NMOS Only PTsSolution 1: Level RestorerTransient Level Restorer Circuit ResponseSolution 2: Multiple VT TransistorsSolution 3: Transmission Gates (TGs)Solution 3: Transmission Gates (TGs)TG MultiplexerTransmission Gate XORTransmission Gate XORTG Full AdderDifferential TG Logic (DPL)Next Time: The MOS TransistorNext Lecture and RemindersCSE477 L07 Pass Transistor Logic.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 07: Pass Transistor LogicMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L07 Pass Transistor Logic.2 Irwin&Vijay, PSU, 2003Review: Static Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPUN and PDN are dual logic networks…… High noise marginsz VOHand VOLare at VDDand GND, respectively Low output impedance, high input impedance No static power consumptionz Never a direct path between VDDand GND in steady state Delay a function of load capacitance and transistor on resistance Comparable rise and fall times (under the appropriate relative transistor sizing conditions)CSE477 L07 Pass Transistor Logic.3 Irwin&Vijay, PSU, 2003Review: Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum!Cout= !Cin(!A v !B) v !A !BCout= Cin(A v B) v A B!Sum = Cout(!A v !B v !Cin) v !A !B !CSum = !Cout(A v B v Cin) v A B CininCSE477 L07 Pass Transistor Logic.4 Irwin&Vijay, PSU, 2003NMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is high Remember - NMOS transistors pass a strong 0 but a weak 1ABXYX = Y if A and BXYABX = Y if A or BCSE477 L07 Pass Transistor Logic.5 Irwin&Vijay, PSU, 2003PMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals PMOS switch closes when the gate input is low Remember - PMOS transistors pass a strong 1 but a weak 0ABXYX = Y if A and B = A + BXYABX = Y if A or B = A • BCSE477 L07 Pass Transistor Logic.6 Irwin&Vijay, PSU, 2003Pass Transistor (PT) LogicABBBFBAF00 Gate is static – a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless Bidirectional (versus undirectional)CSE477 L07 Pass Transistor Logic.7 Irwin&Vijay, PSU, 2003Pass Transistor (PT) LogicABBBBAF= A • BF= A • B00 Gate is static – a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless Bidirectional (versus undirectional)CSE477 L07 Pass Transistor Logic.8 Irwin&Vijay, PSU, 2003VTC of PT AND GateBBF= A•B0.5/0.250.5/0.250.5/0.251.5/0.25012012B=VDD, A=0→VDDA=VDD, B=0→VDDA=B=0→VDDVout, VVin, VA0z Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)CSE477 L07 Pass Transistor Logic.9 Irwin&Vijay, PSU, 2003Differential PT Logic (CPL)ABABPT NetworkFFABABInverse PT NetworkFFF=ABAABF=ABBBBAND/NANDAABF=A+BBF=A+BBBOR/NORAAF=A⊕BF=A⊕BBBXOR/XNORAACSE477 L07 Pass Transistor Logic.10 Irwin&Vijay, PSU, 2003CPL Properties Differential so complementary data inputs and outputs are always available (so don’t need extra inverters) Still static, since the output defining nodes are always tied to VDDor GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. Simple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) Additional routing overhead for complementary signals Still have static power dissipation problemsCSE477 L07 Pass Transistor Logic.11 Irwin&Vijay, PSU, 2003CPL Full AdderAABBCinCin!SumSumCout!CoutABABBB CinCinCinCinCSE477 L07 Pass Transistor Logic.12 Irwin&Vijay, PSU, 2003CPL Full AdderAABBCinCin!SumSumCout!CoutABABBB CinCinCinCinCSE477 L07 Pass Transistor Logic.13 Irwin&Vijay, PSU, 2003NMOS Only PT Driving an InverterIn = VDDA = VDDVx= VDD-VTnM1M2VGSSDB Vxdoes not pull up to VDD, but VDD–VTnThreshold voltage drop causes static power consumption (M2may be weakly conducting forming a path from VDDto GND) Notice VTnincreases for pass transistor due to body effect (VSB)CSE477 L07 Pass Transistor Logic.14 Irwin&Vijay, PSU, 2003Voltage Swing of PT Driving an Inverter01230 0.5 1 1.5 2Time, nsVoltage, VInOutx = 1.8VIn = 0 → VDDVDDxOut0.5/0.250.5/0.251.5/0.25DSB Body effect – large VSBat x - when pulling high (B is tied to GND and S charged up close to VDD) So the voltage drop is even worseVx= VDD-(VTn0+ γ(√(|2φf| + Vx) - √|2φf|))CSE477 L07 Pass Transistor Logic.15 Irwin&Vijay, PSU, 2003Cascaded NMOS Only PTsB = VDDOutM1yM2Swing on y = VDD -VTn1-VTn2xM1B = VDDOutyM2C = VDDA = VDDC = VDDA = VDDx = VDD -VTn1GSGSSwing on y = VDD -VTn1z Pass transistor gates should never be cascaded as on the leftz Logic on the right suffers from static power dissipation and reduced noise marginsCSE477 L07 Pass Transistor Logic.16 Irwin&Vijay, PSU, 2003Solution 1: Level RestorerLevel RestorerM1M2A=0MnMrxBOut =1off= 0A=1Out=0on1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when A is high For correct operation Mrmust be sized correctly (ratioed)CSE477 L07 Pass Transistor Logic.17 Irwin&Vijay, PSU, 2003Transient Level Restorer Circuit Response01230 100 200 300 400 500Voltage, VTime, psW/Lr=1.75/0.25W/Lr=1.50/0.25W/Lr=1.25/0.25W/Lr=1.0/0.25W/Ln=0.50/0.25W/L2=1.50/0.25W/L1=0.50/0.25node x never goes below VMof inverter so output never switches Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases tr(but decreases tf)CSE477 L07 Pass Transistor Logic.18 Irwin&Vijay, PSU, 2003Solution 2: Multiple