CSE477VLSI Digital CircuitsFall 2003 Lecture 23: Semiconductor MemoriesReview: Basic Building BlocksMemory DefinitionsA Typical Memory HierarchyMore Memory DefinitionsRandom Access Read Write Memories (WRMs)Evolution in DRAM Chip Capacity6-transistor SRAM Storage Cell1D Memory Architecture2D Memory Architecture3D (or Banked) Memory Architecture2D 4x4 SRAM Memory BankQuartering Gives Shorter WLs and BLsDecreasing Word Line DelayDecreasing Bit Line Delay (and Energy)Bit Line IsolationPulsed Word LineRead Only Memories (ROMs)MOS OR ROM Cell ArrayMOS OR ROM Cell ArrayPrecharged MOS NOR ROMPrecharged MOS NOR ROMMOS NOR ROM Layout 1MOS NOR ROM Layout 2Transient Model for 512x512 NOR ROMPropagation Delay of 512x512 NOR ROMNonvolatile Read-Write Memories (NVRWM)Next Lecture and RemindersCSE477 L23 Memories.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 23: Semiconductor MemoriesMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L23 Memories.2 Irwin&Vijay, PSU, 2003Review: Basic Building Blocks Datapathz Execution units- Adder, multiplier, divider, shifter, etc.z Register file and pipeline registersz Multiplexers, decoders Controlz Finite state machines (PLA, ROM, random logic) Interconnectz Switches, arbiters, buses Memoryz Caches (SRAMs), TLBs, DRAMs, buffersCSE477 L23 Memories.3 Irwin&Vijay, PSU, 2003Memory Definitions Size – Kbytes, Mbytes, Gbytes, Tbytes Speedz Read Access – delay between read request and the data availablez Write Access – delay between write request and the writing of the data into the memoryz (Read or Write) Cycle - minimum time required between successive reads or writesReadWriteDataRead CycleRead AccessRead AccessWrite CycleData ValidWrite SetupWrite AccessData WrittenCSE477 L23 Memories.4 Irwin&Vijay, PSU, 2003A Typical Memory HierarchyBy taking advantage of the principle of locality, we canz present the user with as much memory as is available in the cheapest technologyz at the speed offered by the fastest technology.SecondLevelCache(SRAM)ControlDatapathSecondaryMemory(Disk)On-Chip ComponentsRegFileMainMemory(DRAM)DataCacheInstrCacheITLBDTLBeDRAMSpeed (ns): .1’s 1’s 10’s 100’s 1,000’sSize (bytes): 100’s K’s 10K’s M’s T’sCost: highest lowestCSE477 L23 Memories.5 Irwin&Vijay, PSU, 2003More Memory Definitions Function – functionality, nature of the storage mechanismz static and dynamic; volatile and nonvolatile (NV); read only (ROM) Access pattern – random, serial, content addressableRead Write Memories (RWM) NVRWM ROMRandom Access Non-Random AccessEPROM Mask-prog. ROMSRAM (cache, register file)DRAM (main memory)CAMFIFO, LIFOShift RegisterEEPROMFLASH Electrically-prog. PROM Input-output architecture – number of data input and output ports (multiported memories) Application – embedded, secondary, tertiaryCSE477 L23 Memories.6 Irwin&Vijay, PSU, 2003Random Access Read Write Memories (WRMs) SRAM – Static Random Access Memoryz data is stored as long as supply is appliedz large cells (6 fets/cell) – so fewer bits/chipz fast – so used where speed is important (e.g., caches)z differential outputs (output BL and !BL) z use sense amps for performancez compatible with CMOS technology DRAM - Dynamic Random Access Memoryz periodic refresh required (every 1 to 4 ms) to compensate for the charge loss caused by leakagez small cells (1 to 3 fets/cell) – so more bits/chipz slower – so used for main memoriesz single ended output (output BL only)z need sense amps for correct operationz not typically compatible with CMOS technologyCSE477 L23 Memories.7 Irwin&Vijay, PSU, 2003642561,0004,00016,00064,000256,0001,000,0004,000,00016,000,00064,000,000101001000100001000001000000100000001000000001980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010YearKbit capacity/chipEvolution in DRAM Chip Capacity1.6-2.4 µm1.0-1.2 µm0.7-0.8 µm0.5-0.6 µm0.35-0.4 µm0.18-0.25 µm0.13 µm0.1 µm0.07 µmhuman memoryhuman DNAencyclopedia2 hrs CD audio30 sec HDTVbookpage4X growth every 3 years!CSE477 L23 Memories.8 Irwin&Vijay, PSU, 20036-transistor SRAM Storage Cell!BL BLWLM1M2M3M4M5M6Q!Q Will cover how the cell works in detail in the next lectureCSE477 L23 Memories.9 Irwin&Vijay, PSU, 20031D Memory ArchitectureWord 0Word 1Word 2Word N-1Word N-2StorageCellM bitsN wordsS0S1S2S3SN-2SN-1Input/OutputN words → N select signalsWord 0Word 1Word 2Word N-1Word N-2StorageCellM bitsS0S1S2S3SN-2SN-1Input/OutputA0A1Ak-1DecoderDecoder reduces # of inputsK = log2NCSE477 L23 Memories.10 Irwin&Vijay, PSU, 20032D Memory ArchitectureA0Row DecoderA1AL-1Sense Amplifiersbit line (BL)word line (WL)storage (RAM) cellRow AddressColumn Address(least significant bits)ALAL+1AK-1Read/Write CircuitsColumn Decoder2K-LM2LInput/Output (M bits)amplifies bit line swingselects appropriate word from memory rowCSE477 L23 Memories.11 Irwin&Vijay, PSU, 20033D (or Banked) Memory ArchitectureRow AddrColumn AddrBlock AddrInput/Output (M bits)A1A0Advantages:1. Shorter word and bit lines so faster access2. Block addr activates only 1 block saving powerCSE477 L23 Memories.12 Irwin&Vijay, PSU, 20032D 4x4 SRAM Memory BankA0Row Decoder!BLWL[0]A1A2Column Decodersense amplifierswrite circuitryBLWL[1]WL[2]WL[3]bit line precharge2 bit wordsclocking and controlenableread prechargeBLiBLi+1CSE477 L23 Memories.13 Irwin&Vijay, PSU, 2003Quartering Gives Shorter WLs and BLsRow DecoderRead PrechargeRead PrechargePrecharge CircuitPrecharge CircuitColumn DecoderSense AmpsColumn DecoderAN-1 …AiAi-1 …A0Write CircuitrySense AmpsWrite CircuitrydataCSE477 L23 Memories.14 Irwin&Vijay, PSU, 2003Decreasing Word Line Delay Drive the word line from both sidespolysilicon word linemetal word linedriverdriverWL Use a metal bypasspolysilicon word linemetal bypassWL Use silicidesCSE477 L23 Memories.15 Irwin&Vijay, PSU, 2003Decreasing Bit Line Delay (and Energy) Reduce the bit line voltage swingz need sense amp for each column to sense/restore signal Isolate sense amps from bit lines after sensing (to prevent the sense amps from changing the bit line voltage further) - bit line isolation Isolate memory cells from the bit lines after sensing (to prevent