Unformatted text preview:

CSE477 L20 Shifters.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 20: Shifters and Other Logicwww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L20 Shifters.2 Irwin&Vijay, PSU, 2001Parallel ShiftersData InControl =Data OutShift amountShift directionShift type (logical,arith, circular)Shifters used in multipliers, floating point unitsLots of area if done in random logic gatesCSE477 L20 Shifters.3 Irwin&Vijay, PSU, 2001A Programmable Binary Shifterrgt nop lftAiAi-1Bi-1Bi0A0100A0A1A10001A0A1A0A1010A0A1Bi-1BilftnoprgtAi-1AiCSE477 L20 Shifters.4 Irwin&Vijay, PSU, 2001A Programmable Binary Shifterrgt nop lftAiAi-1Bi-1Bi0A0100A0A1A10001A0A1A0A1010A0A1Bi-1BilftnoprgtAi-1AiCSE477 L20 Shifters.5 Irwin&Vijay, PSU, 20014-bit Barrel ShifterA0A1A2A3B0B1B2B3Sh1Sh2Sh3Sh0 Sh1 Sh2 Sh3Example: Sh0 = 1B3B2B1B0= A3A2A1A0Sh1 = 1B3B2B1B0= A3A3A2A1Sh2 = 1B3B2B1B0= A3A3A3A2Sh3 = 1B3B2B1B0= A3A3A3A3Area dominated by wiringCSE477 L20 Shifters.6 Irwin&Vijay, PSU, 20014-bit Barrel ShifterA0A1A2A3B0B1B2B3Sh1Sh2Sh3Sh0 Sh1 Sh2 Sh3Example: Sh0 = 1B3B2B1B0= A3A2A1A0Sh1 = 1B3B2B1B0= A3A3A2A1Sh2 = 1B3B2B1B0= A3A3A3A2Sh3 = 1B3B2B1B0= A3A3A3A3Area dominated by wiringCSE477 L20 Shifters.7 Irwin&Vijay, PSU, 20014-bit Barrel Shifter LayoutBufferSh3Sh2Sh1Sh0A3A2A1A0Widthbarrel~ 2 pmNN = max shift distance, pm= metal pitchDelay ~ 1 fet + N diff capsWidthbarrelOnly one Shactive at a timelCSE477 L20 Shifters.8 Irwin&Vijay, PSU, 20018-bit Logarithmic ShifterA3A2A1A0!Sh1Sh1 !Sh2Sh2 !Sh3Sh3B0B1B2B3log N stages0 0 0 111CSE477 L20 Shifters.9 Irwin&Vijay, PSU, 20018-bit Logarithmic ShifterA3A2A1A0!Sh1Sh1 !Sh2Sh2 !Sh3Sh3B0B1B2B3log N stages0 0 0 111CSE477 L20 Shifters.10 Irwin&Vijay, PSU, 20018-bit Logarithmic Shifter Layout SliceWidthlog~ pm(2K+(1+2+…+2K-1)) = pm(2K+2K-1)K = log2NDelay ~ K fets + 2 diff capsA0B3B2B1B0A1A2A31 2 4CSE477 L20 Shifters.11 Irwin&Vijay, PSU, 2001Shifter Implementation Comparisons6 + 25 + 24 + 23 + 2K + 2 diffsSpeed1 + 641 + 321 + 161 + 81 + N diffsSpeed WidthWidthpm(2K+2K-1)2 pmN75 pm41 pm23 pm13 pmLogarithmic128 pm64 pm32 pm16 pmBarrel66453241638KNCSE477 L20 Shifters.12 Irwin&Vijay, PSU, 2001Decodersq Decodes inputs to activate one of many outputsl two inverters, four 2-input nand gates, four inverters plus enable logicl how about for a 3-to-8, 4-to-16, etc. decoder?In0In1EnableOut0 = !In1 & !In0Out1 = !In1 & In0Out2 = In1 & !In0Out3 = In1 & In02x4CSE477 L20 Shifters.13 Irwin&Vijay, PSU, 2001Dynamic NOR DecoderVddGND GNDA0!A0A1!A1B0B1B2B3precharge0 1 0 1CSE477 L20 Shifters.14 Irwin&Vijay, PSU, 2001Dynamic NOR DecoderVddGND GNDA0!A0A1!A1B0B1B2B3precharge0001on ononon0 1 0 1CSE477 L20 Shifters.15 Irwin&Vijay, PSU, 2001Dynamic NAND DecoderGNDA0!A0A1!A1B3prechargeB2B1B0CSE477 L20 Shifters.16 Irwin&Vijay, PSU, 2001Building Big Decoders from Small1x2A4enableA3A22x42x4A1A02x42x4. . .0 0 0 0 11Active high enableCSE477 L20 Shifters.17 Irwin&Vijay, PSU, 2001Multiplexersq Selects one of several inputs to gate to the single outputl two inverters, four 3-input nands, one 4-input nandl how about for an 8x1, 16x1, etc. mux?In0S1S0Out = In0 & !S1 & !S0 |In1 & !S1 & S0 |In2 & S1 & !S0 |In3 & S1 & S0In1In2In34x1CSE477 L20 Shifters.18 Irwin&Vijay, PSU, 2001Transmission Gate 2x1 MultiplexerGNDVDDIn1In2S !S!SSSS!SIn2In1FFF = !(In1 & S | In2& !S)CSE477 L20 Shifters.19 Irwin&Vijay, PSU, 2001Building Big Muxes from SmallA0S0A12x1A2A32x12x1S1Out10CSE477 L20 Shifters.20 Irwin&Vijay, PSU, 2001Building Big Muxes from SmallA0S0A12x1A2A32x12x1S1Out10CSE477 L20 Shifters.21 Irwin&Vijay, PSU, 2001Review: Bit-Sliced ApproachControlRegister FileMultiplexerAdderShifterData InData OutBit 0Bit 1Bit 2Bit 3Tile identical processing elementsCSE477 L20 Shifters.22 Irwin&Vijay, PSU, 2001Layout Strategies for Bit-Sliced DatapathsWellControlWires(M1)WellWires(M1)GNDVDDGNDGNDVDDGNDApproach I —Signal and power lines parallelApproach II —Signal and power lines perpendicularSignals Wires (M2)Signals Wires (M2)CSE477 L20 Shifters.23 Irwin&Vijay, PSU, 2001Layout of Bit-Sliced DatapathsCSE477 L20 Shifters.24 Irwin&Vijay, PSU, 2001Layout of Bit-sliced DatapathsWithout feedthroughs or pitch matching (4.2µm2)With feedthroughs(3.2µm2)With feedthroughs and pitch matching (2.2µm2)CSE477 L20 Shifters.25 Irwin&Vijay, PSU, 2001Alpha 21264 Integer Unit DatapathMultimedia engineShifterIntercluster bypassAdderLogic boxRegister fileRegister file decoderLogic boxAdderIntercluster bypassLoad bypassStore FIFOAddress driverstristate bus driverbus driverRC1_0RC1_1RC2_0RC2_1LSD_1LSD_0to


View Full Document

PSU CSE 477 - Shifters and Other Logic

Download Shifters and Other Logic
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Shifters and Other Logic and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Shifters and Other Logic 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?