1 Logical Effort Sizing Transistors for Speed Estimating Delays  Would be nice to have a “back of the envelope” method for sizing gates for speed  Logical Effort  Book by Sutherland, Sproull, Harris  Chapter 1 is on our web page  Also Chapter 4 in our textbook2 Gate Delay Model  First, normalize a model of delay to dimensionless units to isolate fabrication effects  dabs = d τ  τ is the delay of a minimum inverter driving another minimum inverter with no parasitics  In a 0.6u process, this is approx 40ps  Now we can think about delay in terms of d and scale it to whatever process we’re using Gate Delay  Delay of a gate d has two components  A fixed part called parasitic delay p  A part proportional to the load on the output called the effort delay or stage effort f  Total delay is measured in units of τ, and is sum of these delays  d = f + p3 Effort Delay  The effort delay (due to load) can be further broken down into two terms: f = g * h  g = logical effort which captures properties of the gate’s structure  h = electrical effort which captures properties of load and transistor sizes  h = Cout/Cin  Cout is capacitance that loads the output  Cin is capacitance presented at the input  So, d = gh + p Logical Effort  Logical effort normalizes the output drive capability of a gate to match a unit inverter  How much more input capacitance does a gate need to present to offer the same drive as an inverter? g = 1 g = 4/3 g = 5/34 Computing Logical Effort  DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.  Measure from delay vs. fanout plots  Or estimate by counting transistor widths Logical Effort of Other Gates  Logical effort of common gates assuming that P/N size ratio is 2 Number of inputs5 Electrical Effort  Value of logical effort g is independent of transistor size  It’s related to the ratios and the topology  Electrical effort h captures the drive capability of the transistors via sizing  Electrical effort h = Cout/Cin  Note that as transistor sizes for a gate increase, h decreases because Cin goes up Parasitic Delay  Parasitic delay p is caused by the internal capacitance of the gate  It’s constant and independent of transistor size  As you increase the transistor size, you also increase the cap of the gate/source/drain areas which keeps it constant  For our purposes, normalize pinv to 1  N-input NAND = n*pinv  N-input NOR = n*pinv  N-way mux = 2n*pinv  XOR = 4* pinv6 Plots of Gate Delay Delay Estimation Remember, τ in Our process ~ 40ps ~200ps ~240ps7 Delay Estimation Remember, τ in Our process ~ 40ps ~200ps ~240ps τ in 180nm = ~ 12ps FO4 Inverter delay = 60ps FO4 NAND delay = 72ps Example: Ring Oscillator  Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Period of osc =8 Example: Ring Oscillator  Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 so dabs = 80ps Period: 2*N*dabs = 4.96ns, Freq = ~200MHz For N = 31 Example: FO4 Inverter  Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d =9 Example: FO4 Inverter  Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = gh + p = 5 The FO4 delay is about 200 ps in 0.6 µm process 60 ps in a 180 nm process f/3 ns in an f µm process Delay Estimation  If Cin = x, Cout = 10x, thus h = 10  g = 9/3 = 3  d = gh + p = 3*10 + 4*1 = 34 (1360 ps)10 Multi Stage Delay Off-Path Load Ctotal Cuseful11 Summary – multistage networks  Logical effort generalizes to multistage networks  Path Logical Effort  Path Electrical Effort  Path Effort  Can we write F = GH? Branching Effort  Remember branching effort  Accounts for branching between stages in path  Now we compute the path effort  F = GBH Note:12 Multistage Delays  Path Effort Delay  Path Parasitic Delay  Path Delay Designing Fast Circuits  Delay is smallest when each stage bears same effort  Thus minimum delay of N stage path is  This is a key result of logical effort  Find fastest possible delay  Doesn’t require calculating gate sizes13 Minimizing Path Delay Choosing Transistor Sizes14 Example 0 1 2 minD=N*F 1/N + P = 3*(1.3333) + 6 = 10 Example, continued f(min) = gi * bi * hi15 Transistor Sizes for Example Another Example, Larger Load16 8C Load Example Cont. Example 1.6 from Chap 1 0 1 217 Example 1.6 Continued f(min) = gi * bi * hi Example: 3-stage path  Select gate sizes x and y for least delay from A to B18 Example: 3-stage path Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort Parasitic Delay P = Delay D = Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4.4 FO419 Example: 3-stage path  Work backward for sizes y = x = Example: 3-stage path  Work backward for sizes y = 45 * (5/3) / 5 = 15 (gi*bi*Cout)/fmin= Cin x = (15*2) * (5/3) / 5 = 10 15 4:1 ratio 10 2:3 ratio 8 1:1 ratio f(min) = gi * bi * hi20 Example 1.7 from Chap 1 Note: Don’t care about parasitics for gate sizing, only if you want to know absolute delay… (gi*bi*Cout)/fmin=Cin Misc. Comments  Note that you never size the first gate  This gate is assumed to be fixed  If you were allowed to size it, the algorithm would try to make it as large as possible  This is an estimation algorithm  Authors claim that sizing a gate by 1.5x too big or small still results in a path delay within 15% of minimum21 Sensitivity Analysis  How sensitive is delay to using exactly the best number of stages?  2.4 < ρ <