Logical Effort Sizing Transistors for Speed Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland Sproull Harris Chapter 1 is on our web page Also Chapter 4 in our textbook 1 Gate Delay Model First normalize a model of delay to dimensionless units to isolate fabrication effects dabs d is the delay of a minimum inverter driving another minimum inverter with no parasitics In a 0 6u process this is approx 40ps Now we can think about delay in terms of d and scale it to whatever process we re using Gate Delay Delay of a gate d has two components A fixed part called parasitic delay p A part proportional to the load on the output called the effort delay or stage effort f Total delay is measured in units of and is sum of these delays d f p 2 Effort Delay The effort delay due to load can be further broken down into two terms f g h g logical effort which captures properties of the gate s structure h electrical effort which captures properties of load and transistor sizes h Cout Cin Cout is capacitance that loads the output Cin is capacitance presented at the input So d gh p Logical Effort Logical effort normalizes the output drive capability of a gate to match a unit inverter How much more input capacitance does a gate need to present to offer the same drive as an inverter g 5 3 g 1 g 4 3 3 Computing Logical Effort DEF Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs fanout plots Or estimate by counting transistor widths Logical Effort of Other Gates Logical effort of common gates assuming that P N size ratio is 2 Number of inputs 4 Electrical Effort Value of logical effort g is independent of transistor size It s related to the ratios and the topology Electrical effort h captures the drive capability of the transistors via sizing Electrical effort h Cout Cin Note that as transistor sizes for a gate increase h decreases because Cin goes up Parasitic Delay Parasitic delay p is caused by the internal capacitance of the gate It s constant and independent of transistor size As you increase the transistor size you also increase the cap of the gate source drain areas which keeps it constant For our purposes normalize pinv to 1 N input NAND n pinv N input NOR n pinv N way mux 2n pinv XOR 4 pinv 5 Plots of Gate Delay Delay Estimation Remember in Our process 40ps 200ps 240ps 6 Delay Estimation Remember in Our process 40ps 200ps in 180nm 12ps FO4 Inverter delay 60ps FO4 NAND delay 72ps 240ps Example Ring Oscillator Estimate the frequency of an N stage ring oscillator Logical Effort g Electrical Effort h Parasitic Delay p Stage Delay d Period of osc 7 Example Ring Oscillator Estimate the frequency of an N stage ring oscillator Logical Effort g 1 Electrical Effort h 1 Parasitic Delay p 1 Stage Delay d 2 so dabs 80ps Period 2 N dabs 4 96ns Freq 200MHz For N 31 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter Logical Effort Electrical Effort Parasitic Delay Stage Delay g h p d 8 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter The FO4 delay is about 200 ps in 0 6 m process Logical Effort Electrical Effort Parasitic Delay Stage Delay 60 ps in a 180 nm process g 1 f 3 ns in an f m process h 4 p 1 d gh p 5 Delay Estimation If Cin x Cout 10x thus h 10 g 9 3 3 d gh p 3 10 4 1 34 1360 ps 9 Multi Stage Delay Off Path Load Ctotal Cuseful 10 Summary multistage networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F GH Branching Effort Remember branching effort Accounts for branching between stages in path Note Now we compute the path effort F GBH 11 Multistage Delays Path Effort Delay Path Parasitic Delay Path Delay Designing Fast Circuits Delay is smallest when each stage bears same effort Thus minimum delay of N stage path is This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes 12 Minimizing Path Delay Choosing Transistor Sizes 13 Example 0 minD N F 1 N P 1 2 3 1 3333 6 10 Example continued f min gi bi hi 14 Transistor Sizes for Example Another Example Larger Load 15 8C Load Example Cont Example 1 6 from Chap 1 0 1 2 16 Example 1 6 Continued f min gi bi hi Example 3 stage path Select gate sizes x and y for least delay from A to B 17 Example 3 stage path Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay G H B F P D Example 3 stage path Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay G 4 3 5 3 5 3 100 27 H 45 8 B 3 2 6 F GBH 125 P 2 3 2 7 D 3 5 7 22 4 4 FO4 18 Example 3 stage path Work backward for sizes y x Example 3 stage path f min gi bi hi Work backward for sizes y 45 5 3 5 15 gi bi Cout fmin Cin x 15 2 5 3 5 10 8 1 1 ratio 10 2 3 ratio 15 4 1 ratio 19 Example 1 7 from Chap 1 gi bi Cout fmin Cin Note Don t care about parasitics for gate sizing only if you want to know absolute delay Misc Comments Note that you never size the first gate This gate is assumed to be fixed If you were allowed to size it the algorithm would try to make it as large as possible This is an estimation algorithm Authors claim that sizing a gate by 1 5x too big or small still results in a path delay within 15 of minimum 20 Sensitivity Analysis How sensitive is delay to using exactly the best number of stages 2 4 6 gives delay within 15 of optimal We can be sloppy I like 4 Evaluating Different Options 21 Option 1 Option 2 What if we consider gate area and power What about a 4 input NOR 22 How many stages Consider three alternatives for driving a load 25 times the input capacitance One inverter Three inverters in series Five inverters in series They all do the job but which one is fastest How many stages In all cases G 1 B 1 and H 25 Path delay is N 25 1 N N Pinv N 1 D 26 units N 3 D 11 8 units N 5 D 14 5 units Since N 3 is best each stage will bear an …