Where are we Lots of Layout issues Line of diffusion style Power pitch Bit slice pitch Routing strategies Transistor sizing Wire sizing Layout Line of Diffusion Very common layout method Start with a line of diffusion for each transistor type Cross with poly to make transistors This is the type 2 NOR gate 1 Layout Line of Diffusion Line of Diffusion in General VDD P type N type GND Start with lines of diffusion for each transistor type 2 Line of Diffusion in General VDD P type A B N type GND Cross with Poly to make transistors Line of Diffusion in General VDD P type A B N type GND Now break and connect diffusion There s our NOR gate 3 Line of Diffusion in General VDD P type A B N type GND Now break and connect diffusion There s our NOR gate Stick Diagrams You can plan things with paper and pencil using Stick Diagrams Great for sketchbooks You ll need colored pencils Draw lines for layers instead of rectangles Then you can translate to layout Vdd Y GND A B 4 My Sketchbooks Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut standard height Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 5 Example Inverter Vdd Y GND A Example NAND3 Horizontal N diffusion and p diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40 9 6 x 12 6 Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils A Y Y A B C Wiring Tracks A wiring track is the space required for a wire 1 2 width 1 2 spacing from neighbor results in 2 4 pitch Transistors also consume one wiring track In our rules M1 and M2 width spacing is 3 so pitch is 1 8 7 Well spacing Wells must surround transistors by 1 8u Implies 3 6u 12 between opposite transistor flavors Leaves room for one wire track Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in or by 2 4 to express in microns 8 Example O3AI Sketch a stick diagram for O3AI and estimate area Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y 9 Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y 1 1 A B GND C Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y Y A B C D GND 10 Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y Y A B C D GND Example O3AI Sketch a stick diagram for O3AI and estimate area ABC Y D Vdd Y A B C D GND 11 Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y Y A B C D GND Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y A B C D GND 12 Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Vdd Y A B C D GND Example O3AI Sketch a stick diagram for O3AI and estimate area ABC D Y A B C D 13 Example O3AI Sketch a stick diagram for O3AI and estimate area 14 4 12 Euler Paths A graphical method for planning complex gate layout Take the transistor netlist and draw it as a graph Note that the pull up and pull down trees can be duals of each other Find a path that traverses the graph with the same variable ordering for pull up and pulldown graphs This guides you to a line of diffusion layout 14 Simple example NOR Vdd Vdd A A 1 B B Out Out Out A Vdd 1 B A B A GND 1 B Out GND GND Euler path is a tour of all edges Find a path that has the same ordering for pull up and pull down I e A B Vdd A 1 B Out GND A Out B GND Another great bit of sketchbooking This Path Translates to Layout Find a path that has the same ordering for pullup and pull down e g A B You can also include all the internal nodes Pull up Vdd A 1 B Out Vdd Pull Down GND A Out B GND A Line of diffusion layout 1 B Vdd 1 Out Out A B GND A B GND 15 Examples Switch to chalkboard for examples Hopefully with colored chalk Layout Example Flip Flop Simple D type edge triggered flip flop 16 Zoom in on Latch Need two copies of this for a full D flip flop Zoom in on Latch Need two copies of this for a full D flip flop 17 Zoom in on Latch Need two copies of this for a full D flip flop EN A Y EN Stick Diagram of Latch First add the gates Note where outputs can be shared Ignore details of signal crossings for now 1 2 18 Stick Diagram of Latch First add the gates Note where outputs can be shared Ignore details of signal crossings for now 1 2 Stick Diagram of Latch First add the gates Note where the signals are relative to the schematic 2 1 D 1 2 C Cb 19 Stick Diagram of Latch First add the gates Note where the signals are relative to the schematic Note where additional connections are needed 2 1 D 1 2 C Cb Start With First Enabled Inv I m using 5u power wires 29u vertical picth based on a C5x standard cell model from AMI Probably overkill Add DIF for N and P type transistors Note 2x standard size because of series connection 20 Add Next Enabled Inverter Add two more poly gates for second enabled inverter Note that the two enabled inverters share an output not connected yet Note that I ve added vdd and gnd For DRC I ll deal with C Cb crossover later Aside Multiple Contacts Look at a model of transistor resistance 21 Contact Option 1 Total equivalent resistance 56 1 Ohms Metal resistance 0 05 square Contact resistance 5 contact Active resistance 70 square Gate resistance 50 square Active resistance 7O contact to gate Contact Option 2 Total equivalent resistance 105 1 Ohms 22 Contact Option 3 Total equivalent resistance 24 7 Ohms So put in as many contacts as will fit along side a wide gate Meanwhile Add inverter Note that it s back to standard size Shares vdd gnd connection with enabled inverter Minimum spacing for all transistors so far Incremental DRC at EVERY step 23 Finish Inverter mostly Make inverter output connections Don t connect yet I m going to use M1 as a horizontal layer Which means being careful about vertical use of M1 Make Feedback Connections Output of inverter connected in M1 for now goes …