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U of U CS 6710 - CAD Assignment II

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CS/EE 5710/6710 -- CAD Assignment #2 Due Tuesday, September 17th, 5:00pm Introduction In this CAD assignment you will start physical (mask layout) design. You will implement a schematic and also the physical design that implements the same functionality as the schematic. Physical design is an exacting task, and you ALWAYS need to verify that your layout is correct. You will use two software tools to verify the correctness of your physical design. Design rule checking (DRC) software ensures that your layout obeys the myriad design rules that specify how the different layers interact. The physical design will then be verified structurally against the schematic (used as the specification). This is accomplished with the layout versus schematics (LVS) software. You will then run analog simulation using Spectre to generate analog waveforms from your design. Assignment Tasks 1. Design an inverter using transistors in a Composer schematic and simulate the inverter both with Verilog, and through theAnalog Environment with Spectre. (This is covered in Chapters 3, 4, and 7 in the CAD book). You should also create a symbol view for this inverter. You may want to do this assignment within your CAD1 library that you created in CAD assignment #1 rather than create a new library. You can use nmos, pmos, vdd, and gnd devices from either the NCSU_Analog_Parts or UofU_Analog_Parts libraries. The difference (as described in Chapter 3) is that the NCSU devices have zero delay when simulated by Verilog simulators, and the UofU devices have 0.1ns (100ps) of delay when simulated by Verilog simulators. Analog (Spectre) simulations use accurate transistor models that give detailed delays based on device sizes, loads, and parasitic capacatances. This simulator produces results with analog waveforms. Set the width of the devices in this inverter to be 1.5µ (1.5 microns) for the nmos and 3µ (3 microns) for the pmos. This will be our “unit sized” (minimum sized) inverter for all the design we do in this class. Set the widths when you put the transistors in the schematic or use the “q” properties button to change parameters of transistors that are already in your schematic. The transistor length should be the default (600n which is 600 nanometers (nm) or 0.6 microns). 2. Draw the layout for the inverter in Virtuoso (covered in Chapter 5 of the CAD book). For this layout, and for the NAND gate in part 3 of this assignment you don’t have to use the standard cell template in Chapter 6, but you should think about making the two layouts compatable in terms of (at least) the vdd and gnd connections. Run DRC and LVS to make sure you met the design rules, and that your layout does correspond to the transistorschematic in Part 1. Extract and simulate this inverter with Spectre (i.e. simulate the extracted view). Compare the waveform to the analog waveform from Part 1. Note that you should draw the layout of the transistors to match the widths you used in the schematic. 3. Draw a layout for the two-input NAND gate that you designed in CAD assignment #1. Simulate that layout using Spectre (i.e. simulate the extracted view) and compare against the Verilog simulation from CAD #1. Verify the NAND gate layout with DRC and LVS against the transistor version from CAD #1. The transistor widths you should use are 3µ for both nmos and pmos (update the schematic to match these widths). Why did we pick these widths for the NAND gate? 4. Use the layout of the NAND gate and the layout of the inverter to design the layout version of the function from CAD assignment #1 in Virtuoso. Modify the schematic for the function to use the inverter and NAND instead of only NAND gates. Remember that the function you're implementing is: In the layout you should include instances of the layout for the NAND and layout for the inverter in a new layout view, make the connections by drawing layout to connect them. Remember to connect vdd and gnd as well as the signals. Simulate this layout in Spectre. Verify with DRC and LVS against the modified schematic. Note about LVS logs: You don't need to print out the DRC logs. Note that the layout versus schematic (LVS) verification software will not run successfully unless you have already passed the design rule checking (DRC) software. So you just need to hand in the LVS logs. You can get to the LVS log in two ways. • In the LVS window after you finish the LVS step, you need to press the output button to view the LVS log. In the LVS log window, do a File ->save as and save it to a file. • A log file is generated each time you run LVS called si.out. This file can be found in your ~/VLSI/cadence-f13/LVS directory. This is the same file as in the previous step.Deliverables Like CAD assignment #1, you should make a tar file and hand it in via the handin program. The general form of the command to hand in your data is handin cs6710 <assignment-name> <file-to-hand-in> In this case, if you end up with a tar file called cad2.tar, then the actual command would be: handin cs6710 CAD2 cad2.tar The tar file that you assemble to handin should have the following things in it: • The entire cadence library directory that you used for this assignment. You may do this assignment in your already existing CAD1 library, or create a new CAD2 library. • The *_run1 directories for your Verilog simulation of the inverter, NAND, and Function • The output waveforms from your Spectre simulations of the inverter, NAND, and Function. Make sure to zoom and expand to an interesting part of the waveform before printing the waveform to an output


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