Outline Introduction to CMOS VLSI Design Lecture 2 MIPS Processor Example David Harris Harvey Mudd College Spring 2004 Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design Circuit Design Physical Design Fabrication Packaging Testing 2 MIPS Processor Example Activity 2 CMOS VLSI Design Slide 2 Activity 2 Sketch a stick diagram for a 4 input NOR gate Sketch a stick diagram for a 4 input NOR gate VDD A B C D Y GND 2 MIPS Processor Example CMOS VLSI Design Slide 3 Coping with Complexity How to design System on Chip Many millions soon billions of transistors Tens to hundreds of engineers Structured Design Design Partitioning 2 MIPS Processor Example CMOS VLSI Design 2 MIPS Processor Example CMOS VLSI Design Slide 4 Structured Design Hierarchy Divide and Conquer Recursively system into modules Regularity Reuse modules wherever possible Ex Standard cell library Modularity well formed interfaces Allows modules to be treated as black boxes Locality Physical and temporal Slide 5 2 MIPS Processor Example CMOS VLSI Design Slide 6 1 Design Partitioning Gajski Y Chart Architecture User s perspective what does it do Instruction set registers MIPS x86 Alpha PIC ARM Microarchitecture Single cycle multcycle pipelined superscalar Logic how are functional blocks constructed Ripple carry carry lookahead carry select adders Circuit how are transistors used Complementary CMOS pass transistors domino Physical chip layout Datapaths memories random logic 2 MIPS Processor Example CMOS VLSI Design Slide 7 MIPS Architecture 2 MIPS Processor Example CMOS VLSI Design Slide 8 Instruction Set Example subset of MIPS processor architecture Drawn from Patterson Hennessy MIPS is a 32 bit architecture with 32 registers Consider 8 bit subset using 8 bit datapath Only implement 8 registers 0 7 0 hardwired to 00000000 8 bit program counter 2 MIPS Processor Example CMOS VLSI Design Slide 9 Instruction Encoding CMOS VLSI Design Slide 10 Fibonacci C 32 bit instruction encoding Requires four cycles to fetch on 8 bit datapath format example 6 5 5 5 5 6 R add rd ra rb 0 ra rb rd 0 funct 6 5 5 16 I beq ra rb imm op ra rb imm 6 26 J j dest op dest 2 MIPS Processor Example 2 MIPS Processor Example f0 1 f 1 1 fn fn 1 fn 2 f 1 1 2 3 5 8 13 encoding CMOS VLSI Design Slide 11 2 MIPS Processor Example CMOS VLSI Design Slide 12 2 Fibonacci Assembly Fibonacci Assembly 1st statement n 8 How do we translate this to assembly 2 MIPS Processor Example CMOS VLSI Design Slide 13 Fibonacci Binary Machine language program encoding 6 5 5 5 5 6 0 ra rb rd 0 funct 6 5 5 ra rb 16 I beq ra rb imm op 6 26 J j dest op dest Slide 15 MIPS Microarchitecture Multicycle architecture from Patterson Hennessy PCWriteCond PCEn PCSource PCWrite ALUOp Outputs IorD ALUSrcB 2 MIPS Processor Example CMOS VLSI Design Slide 16 Multicycle Controller Instruction fetch 0 1 MemRead ALUSrcA 0 IorD 0 IRWrite3 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 2 MemRead ALUSrcA 0 IorD 0 IRWrite2 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 3 MemRead ALUSrcA 0 IorD 0 IRWrite1 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 MemRead MemWrite Control Reset RegWrite MemtoReg IRWrite 3 0 ALUSrcA Op 5 0 Memory address computation RegDst 0 Op 5 M 6 Instruction 5 0 Jump address 1 u L B or Op S B Instruction 7 0 Memory data register A B Write data 0 M u x 1 1 Zero ALU ALU result Op L B Read Read register 2 data 1 Registers Write Read register data 2 ALUOut Memory access 6 0 1 M u 2 x 3 Jump completion 12 PCWrite PCSource 10 B Instruction register 0 M Instruction u x 15 11 1 ALUSrcA 1 ALUSrcB 00 ALUOp 01 PCWriteCond PCSource 01 S Write data Instruction 15 0 0 M u x 1 Read register 1 Instruction 20 16 MemData 11 Instruction 25 21 Memory ALUSrcA 0 ALUSrcB 11 ALUOp 00 e Branch completion Execution ALUSrcA 1 ALUSrcB 00 ALUOp 10 Instruction 31 26 Address 9 ALUSrcA 1 ALUSrcB 10 ALUOp 00 x 2 yp R t p 0 M u x 1 8 Op 4 O PC Shift left 2 Instruction decode register fetch MemRead ALUSrcA 0 IorD 0 IRWrite0 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 B EQ CMOS VLSI Design 2 MIPS Processor Example imm Op J add rd ra rb Slide 14 O p example R CMOS VLSI Design Fibonacci Binary 1st statement addi 3 0 8 How do we translate this to machine language Hint use instruction encodings below format 2 MIPS Processor Example Memory access 8 MemRead IorD 1 R type completion 10 MemWrite IorD 1 RegDst 1 RegWrite MemtoReg 0 Write back step 7 ALU control ALUControl RegDst 0 RegWrite MemtoReg 1 Instruction 5 0 2 MIPS Processor Example CMOS VLSI Design Slide 17 2 MIPS Processor Example CMOS VLSI Design Slide 18 3 Logic Design Block Diagram PCWriteCond Start at top level Hierarchically decompose MIPS into units Top level interface 0 M memread aluop 1 0 0 M u x 1 A B Shift left 2 8 Zero ALU ALU result Jump address 1 u x 2 ALU Out 0 1 Write data 1 M u 2 x 3 ALU control ALUControl alucontrol alucontrol 2 0 funct 5 0 irwrite 3 0 regwrite iord regdst memtoreg pcsource 1 0 pcen 8 Read Read register 2 data 1 Registers Write Read register data 2 0 M u x 1 ph1 external memory 8 memdata alusrcb 1 0 reset 6 0 M Instruction u x 15 11 1 Instruction 5 0 controller 8 adr writedata RegDst Read register 1 Instruction 20 16 Instruction 15 0 Instruction register Memory data register alusrca MIPS processor ph2 ALUS rcA RegWrite Op 5 0 Instruction 25 21 Memory Instruction 7 0 memread memwrite ph1 Control Instruction 31 26 Address MemData zero crystal oscillator PCSource P CWrite Outputs ALUOp IorD ALUS rcB M emRead M emWrite MemtoReg IRWrite 3 0 Instruction 5 0 0 M u x 1 Write data op 5 0 2 phase clock generator PCEn PC memwrite ph2 reset datapath adr 7 0 writedata 7 0 memdata 7 0 2 MIPS Processor Example CMOS VLSI Design Slide 19 2 MIPS Processor Example Hierarchical Design alucontrol Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code into gates and layout Requires a library of standard cells datapath standard cell library bitslice fulladder or2 zipper inv4x flop ramslice alu and2 mux4 nor2 inv nand2 Slide 20 HDLs mips controller CMOS VLSI Design mux2 tri 2 MIPS Processor Example CMOS VLSI Design Slide 21 Verilog Example module fulladder input a b c output s cout b sum carry endmodule s1 a b c s c1 a b c cout c CMOS VLSI Design Slide 22 Circuit Design a b c a cout 2 MIPS Processor Example carry sum s fulladder cout s module carry input a b c output cout How should logic be implemented NANDs and NORs vs ANDs