CS ECE 5710 6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different from schematics In schematics you re describing the LOGICAL connections In layout you re describing the PHYSICAL placement of everything Use colored regions to define the different layers that are patterned onto the silicon 1 N type Transistor D G Vgs Vds S i electrons N type from the top Top view shows patterns that make up the transistor 2 Diffusion Mask Mask for just the diffused regions Polysilicon Mask Mask for just the polysilicon areas 3 Diffusion active Mask Diffused active mask is actually drawn as a solid rectangle Polysilicon Mask Polysilicon mask goes on top of the active 4 Combine the two masks You get an N type transistor There are other steps in the process P type transistor Same type of masks as the N type But you have to get the substrate right and you have to dope the diffusion differently 5 General CMOS cross section Note that the general substrate is P type The N substrate for the P transistor is in a well There are lots of other layers Thick SiO2 oxide field oxide Thin SiO2 oxide gate oxide Metal for interconnect Cutaway Photo 6 A Cutaway View CMOS structure with both transistor types and top view structure Top View from that Section Note the different mask layers that correspond to the different transistor layers In particular note the N well and P select layers 7 This is an Inverter In Vdd Gnd Out Layout in Cadence Each color corresponds to a mask layer Draw rectangles to describe mask regions A LOT of things to keep in mind connectivity functionality design rules 8 What are the layers Metal3 Metal2 Metal1 CC Via Via2 Polysilicon Poly Nselect Pselect Nactive Pactive Nwell What are the layers Metal3 Via2 Metal2 Via Metal1 CC Polysilicon Poly Nselect Pselect Nactive Pactive Nwell 9 Photo of Interconnect Back to the Inverter Let s walk through drawing this inverter You can draw layers in whatever order makes sense to you 10 Layout Basics Where poly crosses active transistor For N type nactive over the substrate p substrate For P type pactive inside an Nwell There s really only one active mask nselect and pselect layers define active types Our setup has separate nactive and pactive colors to help keep things straight Layout Basics Diffusion Poly and metal all conduct But resistances are very different Diffusion is worst poly isn t too bad metal is by far the best Contact cuts are needed to connect between layers Make sure to use the right type of contact CC for poly M1 nactive M1 pactive M1 Via1 for M1 M2 Via2 for M2 M3 11 First Layout the Power Rails Power rail pitch is important Allows cells to connect by abutment Also add the N well for the P type transistor Now add Diffusion Note the M1 contacts in the diffusion Diffusion by itself will be N type Diffusion in an N well will be P type Or will it The well just defines the substrate type 12 Add the Select Regions Nselect defines N type diffusion Pselect defines P type diffusion Now add the Poly Gates Remember crossing diffusion with Poly makes a transistor The type of the diffusion and the type of well define what kind of transistor 13 Note the Metal1 Connections Overlapping boxes of the same type of material make a connection Overlaps of different types of material need a contact cut of some sort Connect the Gates Connect gates together to form the inverter Note contact cuts and metal overlaps 14 Layout Subtlety We currently think of transistors as threeterminal devices Gate Source Drain They re really four terminal devices There s also a connection to the substrate It s important to tie the substrate to a specific voltage GND for the P substrate VDD for the N well Make sure PN diodes from active to substrate and well are reverse biased Well or Substrate Contacts Connect P substrate to GND VSS with a little stub of P type diffusion remember pselect Connect the N well to VDD with a little stub of N type diffusion I e inside the N well but with nselect 15 Layout Design Rules Define the allowed geometry of the different layers Guidelines for making safe process masks Rules about the allowed sizes and shapes of a particular layer Rules about how different layers interact Dimensions listed in one of two ways Absolute dimensions e g microns or nm Scalable dimensions in abstract units Usually called lambda Design in lambda units then scale lambda for a particular process Intra Layer Rules Lambda Same Potential Well 12 0 or 6 Different Potential 18 2 3 Contact or Via Hole 2 3 Metal1 Active 3 3 Polysilicon 3 2 2 Select 2 Lambda 0 50 1 0u process Lambda 0 30 0 6u process 3 Metal2 3 4 Metal3 5 16 Intra Layer Rules Native Same Potential 0 or 5 Well 5 Different Potential 5 0 6 0 8 Active 1 Select 0 6 Metal1 Contact or Via Hole 0 8 0 6 Polysilicon 0 6 0 5 0 5 0 7 Metal2 1 0 7 0 7 Metal3 Dimensions are directly in microns Some things scale uniformly others don t Native rules are generally more dense 0 8 Transistor Layout Measurements are in microns based on scalable rules and a lambda of 0 3 17 Vias and Contacts Look at Inverter Layout Again Lots and lots of design rules to consider Use Design Rule Checking DRC to see if everything is OK 18 Layout Design Rules On the class web page Modified version of the MOSIS SCMOS Rev 8 rules Modified to show both Lambda and Micron dimensions All our design will be done in microns Because of the NCSU tech files But even though we re using microns we re using the SCMOS Lambda rules Print them out in color if possible SCMOS Nwell 19 SCMOS Active diffusion SCMOS Poly 20 SCMOS Select SCMOS Contacts 21 SCMOS Contact to Poly SCMOS Contact to Active 22 SCMOS Metal1 SCMOS Via 23 SCMOS Metal2 SCMOS Via2 24 SCMOS Metal3 An Example NOR NOR schematic in Composer 25 First Layout Follow Schematic Note that layout of transistors follows the schematic Two P types in series pulling up Two N types in parallel pulling down Another Layout Better Same four transistors But organized a little differently And sized a little differently 26 Use Shared Source Drain Another Shared S D 27 Two NOR Gates Transistor Sizing We ll get into the details later Consider a transistor s Width and Length Current capability is proportional to W L Length is almost always minimum allowed Change width to change current capability 28 Sizing Rule of Thumb Also P type is about twice as bad as N type Has to do with hole mobility vs