Memory RWM Random Access Non Random Access NVRWM ROM EPROM Mask Programmed 2 E PROM SRAM FIFO DRAM LIFO Programmable PROM FLASH Shift Register CAM Memory Decoders M bits N Words S1 S2 SN 2 SN 1 S0 Word 0 Word 1 Word 2 Storage Cell Word 0 A0 Word 1 A1 Word 2 A K 1 Word N 2 Word N 2 Word N 1 Word N 1 Input Output M bits Input Output M bits N words N select signals Too many select signals Storage Cell Decoder S0 M bits Decoder reduces of select signals K log2N 1 Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits Array Decoding 2 Hierarchical Memory Arrays Row Address Column Address Block Address Global Data Bus Control Circuitry Block Selector Global Amplifier Driver I O Advantages 1 Shorter wires within blocks 2 Block address activates only 1 block power savings Memory Timing Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Write Access Data Valid DATA Data Written 3 Memory Timing Approaches MSB Address Bus LSB Row Address Column Address Address Bus RAS Address Address transition initiates memory operation CAS RAS CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self timed Example HM6264 8kx8 SRAM 4 HM6264 Interface Function Table 5 Timing Read Cycle 1 6 Read Cycle 1 85ns min 85ns max 85ns max 10ns min 85ns max 30ns min 10ns min 45ns max 30ns min 5ns min 30ns min 10ns min Read Cycle 2 7 Read Cycle 2 85ns max 10ns min 10ns min Write Timing 8 Write Cycle Write Cycle 85ns min 75ns min 0ns min 75ns min 55ns min 0ns min 0ns min 30ns max 40ns min 0ns min 9 What Does All This Mean For a read If you assert CS1 CS2 address and OE all at the same time it will be max 85ns before valid data are available at chip outputs For a write You can assert CS1 CS2 address data and WE all at the same time if you want to You need to wait 55ns from WE edge or 75ns from CS1 CS2 edge for write to have happened R W Memories In General STATIC SRAM Data stored as long as supply is applied Large 6 transistors cell Fast Differential DYNAMIC DRAM Periodic refresh required Small 1 3 transistors cell Slower Single Ended 10 SRAM Circuits SRAM Cell Transistors 11 SRAM Resistive Pullups Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits 12 Memory Column Each column has all the support circuits Reading the Bit Single ended read using an inverter Dynamic pre charge on the bit lines P types pull bit lines high 13 Reading the Bit 2 Single ended read using an inverter Dynamic pre charge on the bit lines Note the N types used as pull ups Reading the Bit 3 Differential read using sense amp Static N type pullup on the bit lines 14 Read Waveforms Sense Amp 15 Sense Amp Transistors Column Organization 16 Write Circuits Write Circuit Simulation 0 17 Analog Sim Circuit WL VDD M2 M4 Q M6 Q M5 M1 M3 BL BL Analog Analysis Write WL VDD M4 Q 0 M6 Q 1 M5 M1 VDD BL 1 2 2 VDD VDD V DD VDD k p M4 VDD VTp k n M6 VDD VTn 2 2 8 8 2 kn M5 VDD VDD 2 V DD V DD kn M1 VDD VTn VTn 2 2 2 2 8 BL 0 W L n M6 0 33 W L p M4 W L n M5 10 W L n M1 18 Analog Analysis Read WL VDD M4 BL Q 0 M6 M5 VDD BL Q 1 M1 V DD V DD Cbit C bit VDD V 2 kn M5 V VD D 2 DD D D VTn kn M1 VD D V Tn 2 2 2 2 8 W L n M5 10 W L n M1 supercedes read constraint 6T SRAM Layout 19 Another 6T SRAM Layout SRAM bit from makemem v1 20 SRAM bit from makemem v2 Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits 21 Row Decoders Select exactly one of the memory rows Simple versions are just gates Row Decoder Gates Standard gates Or pseudo nmos gates with static pull up Easier to make large fan in NOR 22 Pre decode Row Decoder Multiple levels of decoding can be more efficient layout Pre decode Row Decoder Other circuit tricks for building row decoders 23 Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits Array Structured Memory 24 Sharing Sense Amps Sense Amp Mux 25 Sense Amp Mux Decoded Column Decode 26 Improving Speed Power Multi Port Memory Very common to require multiple read ports Think about a register file for example 27 Multi Port Register Re1 Re0 Slightly larger cell but with single ended read makes a great register file Register File Slightly larger cell but with single ended read makes a great register file 28 Dynamic RAM Get rid of the pull ups Store info on capacitors Means that stored information leaks away Dynamic RAM Once you agree to use a capacitor for charge storage there are other ways to build this 29 3T DRAM Circuit BL2 BL1 WWL WWL RWL RWL M3 X M1 X VDD VT M2 BL1 VDD BL2 VDD VT CS V No constraints on device ratios Reads are non destructive Value stored at node X when writing a 1 VWWL VTn 3T DRAM Layout BL2 RWL BL1 GND M3 M2 WWL M1 30 1 T DRAM Circuit 2 T 1 T DRAM layout Note the increased gate size of the storage transistor Increases the capacitance 31 1T DRAM Observations 1T DRAM requires a sense amplifier for each bit line due to charge redistribution read out DRAM memory cells are single ended in contrast to SRAM cells The read out of the 1T DRAM cell is destructive read and refresh operations are necessary for correct operation Unlike 3T cell 1T cell requires presence of an extra capacitance that must be explicitly included in the design When writing a 1 into a DRAM cell a threshold voltage is lost This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD 1T …