1MemoryRWMNVRWM ROMEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOMemory DecodersWord 0Word 1Word 2Word N-1Word N-2Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0Word 1Word 2Word N-1Word N-2Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDecoder reduces # of select signalsK = log2NArray-Structured MemoryInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / DriversM.2KProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriatewordArray DecodingHierarchical Memory ArraysGlobal Data BusRowAddressColumnAddressBlockAddressBlock Selector GlobalAmplifier/DriverI/OControlCircuitryAdvantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savingsMemory Timing DefinitionsREADWRITEDATARead AccessRead AccessRead CycleData ValidData WrittenWrite AccessWrite Cycle2Memory Timing ApproachesAddressBusRASCASRAS-CAS timingAddressBusAddressAddress transitioninitiates memory operation DRAM Timing SRAM TimingRow AddressColumn AddressMSB LSBMultiplexed AdressingSelf-timedExample: HM6264 8kx8 SRAMHM6264 Interface Function TableTiming Read Cycle 13Read Cycle 185ns min85ns max85ns max85ns max10ns min10ns min5ns min45ns max10ns min30ns min30ns min30ns minRead Cycle 2Read Cycle 285ns max10ns min10ns minWrite TimingWrite Cycle Write Cycle85ns min75ns min 0ns min75ns min0ns min55ns min0ns min, 30ns max40ns min0ns min4What Does All This MeanFor a read: If you assert CS1, CS2, address, and OE all at the same time, it will be max 85ns before valid data are available at chip outputsFor a write: You can assert CS1, CS2, address, data, and WE all at the same time if you want toYou need to wait 55ns from WE edge, or 75ns from CS1/CS2 edge for write to have happenedR/W Memories In General• STATIC (SRAM)• DYNAMIC (DRAM)Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferentialPeriodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle EndedSRAM Circuits SRAM Cell, TransistorsSRAM, Resistive Pullups Array-Structured MemoryInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / DriversM.2KProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriateword5Memory Column Each column hasall the supportcircuitsReading the BitSingle-ended read using an inverter Dynamic pre-charge on the bit linesP-types pull bit lines highReading the Bit 2Single-ended read using an inverter Dynamic pre-charge on the bit linesNote the N-types used as pull-upsReading the Bit 3Differential read using sense ampStatic N-type pullup on the bit linesRead Waveforms Sense Amp6Sense Amp Transistors Column OrganizationWrite Circuits Write Circuit Simulation0Analog Sim, CircuitVDDQQM1 M3M4M2M5BLWLBLM6Analog Analysis, WriteVDDQ = 1Q = 0M1M4M5BL = 1WLBL = 0M6VDDknM6,VDDVTn–()VDD2-----------VDD28-----------–⎝⎠⎛⎞kpM4,VDDVTp–()VDD2-----------VDD28-----------–⎝⎠⎛⎞=knM5,2-------------VDD2-----------VTnVDD2-----------⎝⎠⎛⎞–⎝⎠⎛⎞2knM1,VDDVTn–()VDD2-----------VDD28-----------–⎝⎠⎛⎞=(W/L)n,M5 ≥ 10 (W/L)n,M1(W/L)n,M6 ≥ 0.33 (W/L)p,M47Analog Analysis, ReadVDDQ = 1Q = 0M1M4M5BLWLBLM6VDDVDDVDDCbitCbitknM5,2---------------VDD2------------VTnVDD2--- ------ ---⎝⎠⎛⎞–⎝⎠⎛⎞2knM1,VDDVTn–()VDD2------------VDD28--- ------ ---–⎝⎠⎛⎞=(W/L)n,M5 ≤ 10 (W/L)n,M1(supercedes read constraint)6T SRAM LayoutAnother 6T SRAM Layout SRAM bit from makemem (v1)SRAM bit from makemem (v2) Array-Structured MemoryInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / DriversM.2KProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriateword8Row DecodersSelect exactly one of the memory rowsSimple versions are just gatesRow Decoder GatesStandard gatesOr, pseudo-nmos gates with static pull upEasier to make large fan-in NORPre-decode Row DecoderMultiple levels of decoding can be more efficient layoutPre-decode Row DecoderOther circuit tricks for building row decoders… Array-Structured MemoryInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / DriversM.2KProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriatewordArray-Structured Memory9Sharing Sense Amps Sense Amp MuxSense Amp Mux Decoded Column DecodeImproving Speed, Power Multi-Port MemoryVery common to require multiple read portsThink about a register file, for example10Multi-Port RegisterRe1Re0Slightly larger cell, but with single-ended read – makes a great register fileRegister FileSlightly larger cell, but with single-ended read – makes a great register fileDynamic RAMGet rid of the pull-ups! Store info on capacitors Means that stored information leaks awayDynamic RAM…Once you agree to use a capacitor for charge storage there are other ways to build this… 3T DRAM CircuitM2M1BL1WWLBL2M3RWLCSXWWLRWLXBL1BL2VDD-VTΔVVDDVDD-VTNo constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn3T DRAM LayoutBL2 BL1WWLRWLM1M2M3GND111 T DRAM Circuit 2-T (1-T) DRAM layoutNote the increased gate size of the storage transistor Increases the capacitance1T DRAM Observations1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD.1T DRAM Read/WriteCSM1BLWLCBLWLXBLVDD−VTVDD/2VDDGNDWrite "1"Read "1"sensingVDD/2ΔVVBLVPRE–VBITVPRE–()CSCSCBL+--- --- - -- -------- - --- - --==Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically around 250 mV.1T DRAM