Memory Memory Decoders M bits ROM S0 Random Access Non Random Access SRAM FIFO DRAM LIFO EPROM Mask Programmed E2PROM Programmable PROM N Words S1 S2 SN 2 FLASH SN 1 M bits S0 Word 0 Word 1 Word 2 Storage Cell Word 0 A0 Word 1 A1 Word 2 AK 1 Storage Cell Decoder NVRWM RWM Word N 2 Word N 2 Word N 1 Word N 1 Input Output M bits Input Output M bits Shift Register CAM N words N select signals Too many select signals Array Structured Memory Decoder reduces of select signals K log2N Array Decoding Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Amplify swing to rail to rail amplitude Sense Amplifiers Drivers A0 Selects appropriate word Column Decoder AK 1 Input Output M bits Hierarchical Memory Arrays Memory Timing Definitions Read Cycle Row Address READ Column Address Read Access Read Access Write Cycle WRITE Block Address Write Access Data Valid Global Data Bus Control Circuitry Block Selector Global Amplifier Driver I O DATA Data Written Advantages 1 Shorter wires within blocks 2 Block address activates only 1 block power savings 1 Memory Timing Approaches MSB Address Bus Example HM6264 8kx8 SRAM LSB Row Address Column Address Address Bus RAS Address Address transition initiates memory operation CAS RAS CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self timed HM6264 Interface Function Table Timing Read Cycle 1 2 Read Cycle 1 Read Cycle 2 85ns min 85ns max 85ns max 10ns min 85ns max 10ns min 45ns max 30ns min 30ns min 5ns min 30ns min 10ns min Read Cycle 2 85ns max 10ns min Write Cycle Write Timing 10ns min Write Cycle 85ns min 75ns min 0ns min 75ns min 55ns min 0ns min 0ns min 30ns max 40ns min 0ns min 3 What Does All This Mean For a read R W Memories In General STATIC SRAM Data stored as long as supply is applied Large 6 transistors cell Fast Differential If you assert CS1 CS2 address and OE all at the same time it will be max 85ns before valid data are available at chip outputs For a write You can assert CS1 CS2 address data and WE all at the same time if you want to You need to wait 55ns from WE edge or 75ns from CS1 CS2 edge for write to have happened DYNAMIC DRAM Periodic refresh required Small 1 3 transistors cell Slower Single Ended SRAM Circuits SRAM Cell Transistors SRAM Resistive Pullups Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits 4 Memory Column Reading the Bit Each column has all the support circuits Single ended read using an inverter Dynamic pre charge on the bit lines P types pull bit lines high Reading the Bit 2 Single ended read using an inverter Dynamic pre charge on the bit lines Note the N types used as pull ups Read Waveforms Reading the Bit 3 Differential read using sense amp Static N type pullup on the bit lines Sense Amp 5 Sense Amp Transistors Column Organization Write Circuits Write Circuit Simulation 0 Analog Sim Circuit Analog Analysis Write WL WL VDD VDD M2 M4 M4 Q 0 Q M6 Q 1 M5 M6 Q M5 M1 VDD BL 1 M1 BL BL 0 M3 BL 2 2 VDD VDD VDD VDD k n M6 VDD VTn k p M4 VDD VTp 2 2 8 8 2 2 VDD kn M5 VDD VDD V DD VTn kn M1 VDD VTn 2 2 2 2 8 W L n M6 0 33 W L p M4 W L n M5 10 W L n M 1 6 Analog Analysis Read 6T SRAM Layout WL VDD M4 BL Q 0 M5 V DD BL M6 Q 1 M1 VDD VDD Cbit C bit kn M5 V VD D 2 VDD V 2 DD D D VTn kn M1 VD D V Tn 2 2 2 2 8 supercedes read constraint Another 6T SRAM Layout SRAM bit from makemem v1 SRAM bit from makemem v2 Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH 2L K AK AK 1 AL 1 Bit Line Storage Cell Row Decoder W L n M5 10 W L n M1 Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits 7 Row Decoders Row Decoder Gates Select exactly one of the memory rows Standard gates Or pseudo nmos gates with static pull up Easier to make large fan in NOR Simple versions are just gates Pre decode Row Decoder Pre decode Row Decoder Multiple levels of decoding can be more efficient layout Other circuit tricks for building row decoders Array Structured Memory Array Structured Memory Problem ASPECT RATIO or HEIGHT WIDTH AK AK 1 AL 1 Bit Line Storage Cell Row Decoder 2L K Word Line M 2K Sense Amplifiers Drivers A0 Column Decoder AK 1 Amplify swing to rail to rail amplitude Selects appropriate word Input Output M bits 8 Sharing Sense Amps Sense Amp Mux Sense Amp Mux Decoded Column Decode Improving Speed Power Multi Port Memory Very common to require multiple read ports Think about a register file for example 9 Multi Port Register Register File Re1 Re0 Slightly larger cell but with single ended read makes a great register file Slightly larger cell but with single ended read makes a great register file Dynamic RAM Dynamic RAM Get rid of the pull ups Store info on capacitors Means that stored information leaks away Once you agree to use a capacitor for charge storage there are other ways to build this 3T DRAM Circuit 3T DRAM Layout BL2 BL1 BL2 WWL WWL BL1 GND RWL RWL RWL M3 X M1 X M3 VDD VT M2 M2 BL1 VDD BL2 VDD VT CS V WWL M1 No constraints on device ratios Reads are non destructive Value stored at node X when writing a 1 VWWL VTn 10 1 T DRAM Circuit 2 T 1 T DRAM layout Note the increased gate size of the storage transistor Increases the capacitance 1T DRAM Observations 1T DRAM requires a sense amplifier for each bit line due to charge redistribution read out 1T DRAM Read Write BL WL Write 1 DRAM memory cells are single ended in contrast to SRAM cells M1 The read out of the 1T DRAM cell is destructive read and refresh operations are necessary for correct operation CS X When writing a 1 into a DRAM cell a threshold voltage is lost This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD CBL VDD VT GND VDD BL Unlike 3T cell 1T cell requires presence of an extra capacitance that must be explicitly included in the design Read 1 WL VDD 2 sensing VDD 2 Write CS …