Using makemem template V1 2 November 18 2004 Modified by Erik Brunvand for CS EE 6710 Nov 2006 This document describes how to set up to use makemem the ROM and SRAM generator It also gives an example of creating each type of file Required directories and files 1 First you need to edit your library path to point to the memCells library that contains all the pieces that makemem will use to create your memory structure Edit your library path using the library manager Edit Library Path or by editing your cds lib file to include the following new library memCells uusoc facilities cad common local Cadence lib mem memCells 2 For EACH new memory that you want to build you need to create a new Cadence library to hold that memory This is because the makemem program generates a LOT of stuff in the library that holds your memory and you don t want it cluttering up your main cell library or your project library If you make a new library for each memory then you can include your memory circuit into your project out of that new library and you won t mess up your primary library For this example of a ROM I ll create a library named rom64x32 Make sure to attach the UofU TechLib ami06 technology to your new library 3 Now you need to make a unix directory in which to run makemem This is because of the same issue makemem creates files that you want to keep localized in a directory For this example I ll create a directory called IC CAD mem 4 Before you start you need to copy some files into your new IC CAD mem directory From uusoc facilities cad common local Cadence lib mem cif copy memCells cif and memCells v to your IC CAD mem directory 5 Now for an example ROM definition file copy uusoc facilities cad common local Cadence lib mem examples ROMfiles R64x32 rom to your IC CAD mem directory Allen Tanner CS5710 CS6710 Now you will use the makemem java program to create the files for your ROM makemem creates ROM files for Cadence 1 cd IC CAD mem use the working directory 2 java cp uusoc facility cad common local Cadence lib mem j makemem h The h gets the help message to check if things are set up properly 3 java cp uusoc facility cad common local Cadence lib mem j makemem r R64x32 4 makemem will reproduce the binary contents of the ROM file R64x32 rom on the console log You should look to see if it is the data from the file 5 makemem will produce three files R64x32 cif R64x32 v R64x32 il CIF file for layout import verilog file for schematic import Cadence SKILL code file for IO pin attachment Your files will need to be brought into the CADENCE database The following three procedures will read your files in CIF IN 1 2 3 4 5 6 7 8 creates a structure layout Make a new Cadence library to hold your new ROM I ll call mine R64x32 CIW File Import CIF Run directory IC CAD mem Input file IC CAD mem R64x32 cif Top Cell name leave blank this tells it to use the structure cell as the top cell name leaving it blank will bring in all the cells Library name your new library to hold these cells i e R64x32 if that s what you named it Make sure the option Do not over write cell views is not asserted this is inside the options menu and should be set correctly unless you change it so you probably don t have to worry You should get a notice that PIPO CIFIN has completed with no errors or warnings Actually you ll probably get one warning that you didn t assert the Do Not Over Write Cell Views option But since this is the way you wanted things set this is ignorable The PIPO LOG file will be in the directory you chose as your run directory IC CAD mem in this case Verilog IN 1 CIW File Import Verilog 2 Target library name R64x32 3 Reference libraries memCells remove sample basic Allen Tanner CS5710 CS6710 4 5 6 7 Verilog files to import IC CAD mem R64x32 v v Options IC CAD mem memCells v Make sure that the following is enabled Overwrite existing views You should see Verilog import completed using the memCells versions of the cells Note that you have to have added the memCells library to your library path for this to work with no errors You now have two layouts SR64x32 RR64x32 in the library There is also a schematic and symbol for the combined layout All of these should reside in the library R64x32 When you make changes to the ROM contents and re run the processing steps you will get new RR64x32 layout and a new SR64x32 schematic and symbol the symbol will be new but it won t change unless the structure changes then of course you will also need a new SR64x32 layout The generated ROM is in two parts SR64x32 which is the decoder and the support structure for the ROM and RR64x32 which is the ROM contents This is so that once you put the ROM into a larger layout you can replace the contents to fix a bug for example just by replacing the dockable ROM contents within the ROM structure But it also means you need to assemble these pieces before you have a working ROM Now use CADENCE to assemble your generated layout Layout 1 Open the layout view of SR64x32 2 Insert an instance of RR64x32 at exactly X 0 0 and Y 0 0 Use the controls at the top of Virtuoso to guide you You will probably want to zoom into the origin for fine control 3 Save the new combined layout You want the cell origin when you use the q properties key to be at 0 0 The RR cell overlaps the nor decoder by 3 9 um and the top row of pup pullups by 1 2um 4 Use DRC to check to see if RR64x32 is in the right place 5 Place the IO pins into the design Add IO pins to your layout IO Pins 1 The next step is to put I O pins into the layout Have the SR64x32 layout open when you do these steps 2 CIW window command field load IC CAD mem R64x32 il 3 This will return a t no quotes if it is successful 4 CIW window make pads R64x32 SR64x32 R64x32 is the library name SR64x32 is the overall ROM layout cellview name 5 This will place all of the IO pads into the layout It also returns a dbxxxxxx if successful which is the reference to the database object that was updated 6 If it fails you can use undo in the layout view to reverse the action 7 Use DRC Extract LVS tools to check everything Allen Tanner CS5710 CS6710 At this point you will have complete layout schematic and symbol …