CPR E 465 LABORATORY Tutorial Lab 1 v1 1 Behavioral Modeling Simulation Week 2 Authored by Hon Chi Ng ECpE Dept Iowa State University Modified by Charlie Boecker for Cadence v4 4 1 0 Introduction In the first part of this lab you will learn how to create library cells and cellviews in Cadence s design database called Design Framework II DFII Next you will learn how to design circuits abstractly through behavioral modeling as well as hierarchically through structural modeling Behavioral modeling is described through hardware description language HDL Currently the 2 dominant general purpose HDLs are Verilog HDL and VHDL VHSIC HDL You will learn one of them namely Verilog and simulate your designs using Cadence s Verilog XL simulator 1 Design Management with Design Framework II DFII 1 1 Now let us create a directory called cadence We will store all our designs of all the labs in the cadence directory mkdir cadence cd cadence To run Cadence cadence After a few seconds a CIW Command Interpreter Window should appear Later a Welcome to Cadence 4 4 1 dialog box will appear Along with the Welcome to Cadence 4 4 1 a What s New box will appear Click on Close button after reading the content of the Welcome to Cadence 4 4 1 box Then in the What s New box go to View Off at Startup TI something from this step needs to be turned in Q there is a question in the back that refers to this step Copyright 1997 Hon Chi Ng Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage provided this copyright message is accompanied in all the duplicates distributed All other rights reserved All Cadence s tools referred are trademarks or registered trademarks of Cadence Design Systems Inc All other trademarks belong to their respective owners Cpr E 465 Laboratory Tutorial Lab 1 v1 1 Behavioral Modeling and Simulation Page 2 of 47 Click on YES in the Turn off What s New at Startup window that pops up This will disable the display of the box when you log in next time As conventions for the rest of this handout and upcoming handouts LMB stands for left mouse button Likewise MMB and RMB stand for middle mouse button and right mouse button respectively 1 2 Cadence keeps all its designs in database format called Design Framework II DFII The top level organization is called library Each library has a technology described in the technology file associated with it All designs within the library are based on the same technology file Before we start creating a new design library let us look at what the default libraries that are available In CIW choose Tools Library Manager In Library Manager window there are some libraries supplied as default Only those libraries prefixed with 465 will be used for our labs namely 465ref and 465Pads 465pads12 We will hereafter refer these libraries as reference libraries Pay no attention to other libraries Let us go to 465ref library by clicking on it using the left mouse button LMB We want to see the different categories available in the library so we need to click on the Show Categories button in the Library Manager You will see a few categories listed under 465ref library Within these categories there is more sub categories or cells For example Gates category contains sub categories like ANDs NANDs NORs ORs XNORs and XORs and cells like buffer and inv Within ANDs category it contains cells like and2 and3 and4 and5 and and6 Each of these cells has 2 different cellviews namely symbol and verilog So far you have been introduced to the terms library category cell and cellview Category allows us to organize our designs within a given library Cell is the actual design Each cell can have multiple cellviews the representations of the design The analogy is think of library as user account category as directory cell as file and cellview as format I know it is kind of awkward to have a file with multiple formats but this is the best analogy I can think of 1 3 Now let us create a library named cpre465 The technology file we will use is written for MOSIS Orbit 2 0m N well double poly double metal CMOS process which complies with MOSIS SCMOS Scalable CMOS Design Rules Hence l 1 0m NOTE All the libraries should be created using File New Library under the CIW there is also a File New Library command under the Library Manager If you use the second method the Library won t be created correctly so don t use it In CIW choose File New Library In the New Library form type cpre465 in Library Name field The path should be home user cadence In the Technology File field click on Attach to an existing techfile Click on OK An Attach Design Library to Technology File Last Updated 01 11 99 9 54 AM Cpr E 465 Laboratory Tutorial Lab 1 v1 1 Behavioral Modeling and Simulation Page 3 of 47 form should appear Since we will use the digital version of MOSIS Orbit 2 0 m technology choose Orbit20digital for the Attach to Technology Library field Click on OK The technology is being attached and the status is shown in CIW Upon completion CIW will display the message Created library cpre465 as home user cadence cpre465 Design library cpre465 successfully attached to technology library Orbit20digital You will also notice that cpre465 library is now listed within Library Manager window along with other reference libraries Click the left mouse button LMB on cpre465 library we just created Nothing is under it yet but that will definitely change 2 Concurrency of Hardware HDL How does Hardware Description Language HDL differ from general programming languages In another words why can t general programming languages be used to described digital circuits Concurrency Separate parts of a hardware can simultaneously operate either dependently or independently whereas a software program flows sequentially As a side question can multithreading in programming languages address such concurrency of hardware HDL also provides other features constructs syntax to allow designers to describe digital circuits more naturally and conveniently 2 1 Design Concept using Verilog HDL Before we learn how to describe designs in behavioral modeling let us study some concepts in Verilog a Module Module also referred as block or entity is the basic unit of a circuit design It contains logical functionality that is specified internally and exhibited through its inputs and outputs port interface to other modules external world By grouping the functionality into a module and allowing