CS EE 5710 6710 Cadence V5 to V6 conversion notes Digitial VLSI Chip Design CAD manual Chapter 1 There are no significant V6 issues with Chapter 1 that I know about The only minor one is that Verilog XL is not used as a mainline Verilog simulator any more NC Verilog is the recommended Verilog simulator in V6 Chapter 2 There are only very minor V6 issues with Chapter 2 The Command Interpreter Window CIW and Library Manager windows look ever so slightly different The new windows look like the following Figure a Figure 2 1 from the text Figure b Figure 2 2 from the text Chapter 3 The Composer tool works very much the same as described in the text but the interface in V6 looks a little different Also the integration with Verilog XL has been removed NC Verilog is the preferred Verilog simulator in V6 Here are some V6 versions of the figures from the book Figure c Figure 3 1 in the text Figure d Figure 3 2 in the text In section 3 2 1 In the text is says Add Instance In the V6 menus this is Create Instance In fact all the menu choices listed as in the Add menu in the text are in the Create menu in V6 wire pin and note specifically For the sheet titles use Edit SheetTitle In section 3 2 2 the symbol can be created with Create Cellview FromCellview You can exit Composer with File CloseAll In section 3 4 you print your schematic with File Print The following are V6 versions of the figures from Chapter 3 Note that most of them are almost identical to the versions in the text but I ll include them here just in case there are subtle differences The main difference is that the main Composer window has a component browser on the left side and an enhanced set of function widgets along the top Figure e Figure 3 3 from the text I think the main dialog boxes that you see when using Composer look very much the same as in V5 but I ll include some screen captures here just in case Figure f Figure 3 4 from the text Figure g Figure 3 5 from the text Figure h Figure 3 6 from the text Figure i Figure 3 7 from the text You can see the new instance browser on the left side of the window This lets you select components by name in the schematic Figures 3 8 and 3 9 in the text are pretty much the same in V6 Figure j Figure 3 10 from the text Figure k figure 3 13 from the text Figures 3 15 and 3 16 for plotting look very similar to the V5 figures in the text Chapter 4 The biggest change in Chapter 4 is that the Verilog XL simulator is not recommended any more so the automatic integration with Composer is now with NC Verilog Verilog XL was very specifically a Verilog 1995 simulator It would not interpert any Verilog code that was not included in the 1995 standard NC Verilog includes all the new Verilog 2001 features and is the mainline simulator that will continue to be upgraded to new versions of Verilog So you can safely skip all the stuff in Chapter 4 related to Verilog XL In section 4 1 2 there are only mild differences between the V5 and V6 interfaces to NC Verilog Here are some of the figures that are different enough for you to notice anything Figure l Figure 4 24 in the text Notice that you are also allowed to change the TestBench file in this version of the dialog In practice you should not have to change either of the files names in this dialog box Figure m Figure 4 28 in the text The only difference here is that you can give the new file a type You probably won t have to worry too much about this label You should make sure that the type matches what you expect this cell view to be In practice the tool is pretty good at getting the default correct The other figures in Chapter 4 should be similar enough to not cause any problems Chapter 5 The main Virtuoso window will look a bit different in V6 The main window is shown here The main differences are that it now includes the Layer Selection Window as a pane on the left part of the Virtuoso window rather than as a separate window Also there are extra command widgets both on the top and bottom of the window You can hover your mouse over those to see what they do Figure n This doesn t correspond with any particular figure in the text It should probably come before Figure 5 4 in the text When you get to page 116 where the text talks about creating a contact you need to substitute Create Via instead in V6 The Create Via dialog box is a little fancier than what is shown in Figure 5 6 in the text Mostly you can ignore the extra fancieness and just select the via that you want and the rows and columns that you wns if you re making a multiple cut via Figure o Figure 5 6 in the text In the Create Path dialog Figure 5 12 I haven t played with paths enough to know how to set the Change to Layer option or whether that still works In the Shape Pin dialog box Figure 5 16 the main change is that addition of the Connectivity button that has to do with the router that you might use later You should probably leave the connectivity to the default of Strong In section 5 4 1 on design rule checking the dialog for finding all the DRC errors has a few more choices of what type of errors to be interested in This can help you narrow down what you re looking for more quickly Figure p Figure 5 27 in the text In section 5 5 on the Extraction LVS process the biggest change is that when the LVS process reports completion it also reports the result of the LVS This is a very nice change Figure q Figure 5 35 from the text Chapter 6 There should be very few V6 issues with Chapter 6 The overall template measurements for the UofU standard cell template have not changed Chapter 7 The Spectre simulator itself has not changed much in V6 There are two new interfaces for the Analog Design Environment ADE though The one we used in V5 is now called ADE L and is the one you should use if you re following along with the text ADE XL and ADE GXL are not covered in the CAD text The interaction with ADE L is largely the same as described in the text The waveform window has a few enhancements like better notation of what signals the waveforms represent on the left of the window and a preview view of the waveform in the small window …