Estimating Delays Gate Delay Model Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort First normalize a model of delay to dimensionless units to isolate fabrication effects dabs d is the delay of a minimum inverter driving another minimum inverter with no parasitics In a 0 6u process this is approx 40ps Now we can think about delay in terms of d and scale it to whatever process we re building the circuit in Book by Sutherland Sproull Harris Chapter 1 is on our web page Also Chapter 4 in our textbook Gate Delay Effort Delay Delay of a gate d has two components The effort delay due to load can be further broken down into two terms A fixed part called parasitic delay p A part proportional to the load on the output called the effort delay or stage effort f Total delay is measured in units of and is sum of these delays d f p f g h g logical effort which captures properties of the gate s structure h electrical effort which captures properties of load and transistor sizes h Cout Cin Cout is capacitance that loads the output Cin is capacitance presented at the input So d gh p Computing Logical Effort Logical Effort Logical effort normalizes the output drive capability of a gate to match a unit inverter How much more input capacitance does a gate need to present to offer the same drive as in inverter g 5 3 g 1 DEF Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs fanout plots Or estimate by counting transistor widths g 4 3 1 Logical Effort of Other Gates Logical effort of common gates assuming that P N size ratio is 2 Electrical Effort Value of logical effort g is independent of transistor size It s related to the ratios and the topology Number of inputs Electrical effort h captures the drive capability of the transistors via sizing Electrical effort h Cout Cin Note that as transistor sizes for a gate increase h decreases because Cin goes up Parasitic Delay Plots of Gate Delay Parasitic delay p is caused by the internal capacitance of the gate It s constant and independent of transistor size As you increase the transistor size you also increase the cap of the gate source drain areas which keeps it constant For our purposes normalize pinv to 1 N input NAND n pinv N input NOR n pinv N way mux 2n pinv XOR 4 pinv Delay Estimation Delay Estimation Remember in Our process 40ps Remember in Our process 40ps 200ps 200ps 240ps in 180nm 12ps FO4 Inverter delay 60ps FO4 NAND delay 72ps 240ps 2 Example Ring Oscillator Estimate the frequency of an N stage ring oscillator Logical Effort g Electrical Effort h Parasitic Delay p Stage Delay d Period of osc Example Ring Oscillator Estimate the frequency of an N stage ring oscillator Logical Effort g 1 Electrical Effort h 1 Parasitic Delay p 1 Stage Delay d 2 so dabs 80ps Period 2 N dabs 4 96ns Freq 200MHz Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter The FO4 delay is about 200 ps in 0 6 m process Logical Effort Electrical Effort Parasitic Delay Stage Delay g h p d Delay Estimation Logical Effort Electrical Effort Parasitic Delay Stage Delay g 1 60 ps in a 180 nm process f 3 ns in an f m process h 4 p 1 d gh p 5 Multi Stage Delay If Cin x Cout 10x thus h 10 g 9 3 3 d gh p 3 10 4 1 34 1360 ps 3 Summary multistage networks Off Path Load Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Ctotal Cuseful Path Effort Can we write F GH Branching Effort Remember branching effort Accounts for branching between stages in path Note Multistage Delays Path Effort Delay Path Parasitic Delay Path Delay Now we compute the path effort F GBH Designing Fast Circuits Minimizing Path Delay Delay is smallest when each stage bears same effort Thus minimum delay of N stage path is This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes 4 Choosing Transistor Sizes Example 0 1 2 minD N F 1 N P Example continued Transistor Sizes for Example Another Example Larger Load 8C Load Example Cont 5 Example 1 6 from Chap 1 0 1 Example 1 6 Continued 2 Example 3 stage path Example 3 stage path Select gate sizes x and y for least delay from A to B Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay Example 3 stage path Logical Effort G 4 3 5 3 5 3 100 27 Electrical Effort H 45 8 Branching Effort B 3 2 6 Path Effort F GBH 125 Best Stage Effort Parasitic Delay P 2 3 2 7 Delay D 3 5 7 22 4 4 FO4 G H B F P D Example 3 stage path Work backward for sizes y x 6 Example 3 stage path Example 1 7 from Chap 1 Work backward for sizes y 45 5 3 5 15 gi Cout fmin Cin x 15 2 5 3 5 10 gi Cout fmin Cin Note Don t care about parasitics for gate sizing only if you want to know absolute delay Misc Comments Note that you never size the first gate This gate is assumed to be fixed If you were allowed to size it the algorithm would try to make it as large as possible Sensitivity Analysis How sensitive is delay to using exactly the best number of stages This is an estimation algorithm Authors claim that sizing a gate by 1 5x too big or small still results in a path delay within 15 of minimum 2 4 6 gives delay within 15 of optimal We can be sloppy I like 4 Evaluating Different Options Option 1 7 Option 2 How many stages Consider three alternatives for driving a load 25 times the input capacitance One inverter Three inverters in series Five inverters in series They all do the job but which one is fastest How many stages In all cases G 1 B 1 and H 25 Path delay is N 25 1 N N Pinv N 1 D 26 units N 3 D 11 8 units N 5 D 14 5 units Choosing the Best of Stages You can solve the delay equations to determine the number of stages N that will achieve the minimum delay Approximate by Log4F Since N 3 is best each stage will bear an effort of 25 1 3 2 9 So each stage is 3x larger than the last In general the best stage effort is between 3 and 4 not e as often stated The e value doesn t use parasitics Example String of …