1Introduction toCMOS VLSIDesignLecture 5: Logical EffortDavid HarrisHarvey Mudd CollegeSpring 20045: Logical Effort Slide 2CMOS VLSI DesignOutline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary5: Logical Effort Slide 3CMOS VLSI DesignIntroduction Chip designers face a bewildering array of choices– What is the best circuit topology for a function?– How many stages of logic give least delay?– How wide should the transistors be? Logical effort is a method to make these decisions– Uses a simple model of delay– Allows back-of-the-envelope calculations– Helps make rapid comparisons between alternatives– Emphasizes remarkable symmetries? ? ?5: Logical Effort Slide 4CMOS VLSI DesignExample Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications:– 16 word register file– Each word is 32 bits wide– Each bit presents load of 3 unit-sized transistors– True and complementary address inputs A[3:0]– Each input may drive 10 unit-sized transistors Ben needs to decide:– How many stages to use?– How large should each gate be?– How fast can decoder operate?A[3:0] A[3:0]1632 bits16 words4:16 DecoderRegister File5: Logical Effort Slide 5CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unitabsddτ=τ = 3RC≈ 12 ps in 180 nm process40 ps in 0.6 µm process5: Logical Effort Slide 6CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unit Delay has two componentsabsddτ=dfp=+25: Logical Effort Slide 7CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f =gh(a.k.a. stage effort)– Again has two componentsabsddτ=dpf=+5: Logical Effort Slide 8CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort)– Again has two components g: logical effort– Measures relative ability of gate to deliver current– g ≡ 1 for inverterabsddτ=dfp=+5: Logical Effort Slide 9CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort)– Again has two components h: electrical effort = Cout/ Cin– Ratio of output to input capacitance– Sometimes called fanoutabsddτ=dfp=+5: Logical Effort Slide 10CMOS VLSI DesignDelay in a Logic Gate Express delays in process-independent unit Delay has two components Parasitic delay p– Represents delay of gate driving no load– Set by internal parasitic capacitanceabsddτ=dpf=+5: Logical Effort Slide 11CMOS VLSI DesignDelay Plotsd = f + p= gh + pElectrical Ef f o r t:h = Cout / CinNormalized Delay: dInv erter2-inputNANDg =p =d =g =p =d =01234501234565: Logical Effort Slide 12CMOS VLSI DesignDelay Plotsd = f + p= gh + p What about NOR2?Electrical Ef f o r t:h = Cout / CinNormalized Delay: dInv erter2-inputNANDg = 1p = 1d = h + 1g = 4/3p = 2d = (4/3)h + 2Ef f o r t Delay : fParasitic Delay: p012345012345635: Logical Effort Slide 13CMOS VLSI DesignComputing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widthsAYABYABY1211222244Cin = 3g = 3/3Cin = 4g = 4/3Cin = 5g = 5/35: Logical Effort Slide 14CMOS VLSI DesignCatalog of Gates8, 16, 16, 86, 12, 64, 4XOR, XNOR22222Tristate / mux(2n+1)/39/37/35/3NOR(n+2)/36/35/34/3NAND1Invertern4321Number of inputsGate type Logical effort of common gates5: Logical Effort Slide 15CMOS VLSI DesignCatalog of Gates864XOR, XNOR2n8642Tristate / muxn432NORn432NAND1Invertern4321Number of inputsGate type Parasitic delay of common gates– In multiples of pinv(≈1)5: Logical Effort Slide 16CMOS VLSI DesignExample: Ring Oscillator Estimate the frequency of an N-stage ring oscillatorLogical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =Frequency: fosc= 5: Logical Effort Slide 17CMOS VLSI DesignExample: Ring Oscillator Estimate the frequency of an N-stage ring oscillatorLogical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay: d = 2Frequency: fosc= 1/(2*N*d) = 1/4N31 stage ring oscillator in 0.6 µm process has frequency of ~ 200 MHz5: Logical Effort Slide 18CMOS VLSI DesignExample: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =d45: Logical Effort Slide 19CMOS VLSI DesignExample: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay: d = 5dThe FO4 delay is about200 ps in 0.6 µm process60 ps in a 180 nm processf/3 ns in an f µm process5: Logical Effort Slide 20CMOS VLSI DesignMultistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path EffortiGg=∏out-pathin-pathCHC=iiiFfgh==∏∏10xyz20g1 = 1h1 = x/10g2 = 5/3h2 = y/xg3 = 4/3h3 = z/yg4 = 1h4 = 20/z5: Logical Effort Slide 21CMOS VLSI DesignMultistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH?iGg=∏out pathin pathCHC−−=iiiFfgh==∏∏5: Logical Effort Slide 22CMOS VLSI DesignPaths that Branch No! Consider paths that branch:G =H =GH =h1=h2=F = GH?5151590905: Logical Effort Slide 23CMOS VLSI DesignPaths that Branch No! Consider paths that branch:G = 1H = 90 / 5 = 18GH = 18h1= (15 +15) / 5 = 6h2= 90 / 15 = 6F = g1g2h1h2= 36 = 2GH5151590905: Logical Effort Slide 24CMOS VLSI DesignBranching Effort Introduce branching effort– Accounts for branching between stages in path Now we compute the path effort–F = GBHon path off pathon pathCCbC+=iBb=∏ihBH=∏Note:55: Logical Effort Slide 25CMOS VLSI DesignMultistage Delays Path Effort Delay Path Parasitic Delay Path DelayFiDf=∑iPp=∑iFDdDP==+∑5: Logical Effort Slide 26CMOS VLSI DesignDesigning Fast Circuits Delay is smallest when each stage bears same effort Thus minimum delay of N stage path is This is a key result of logical