Outline Introduction to CMOS VLSI Design Lecture 5 Logical Effort Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary David Harris Harvey Mudd College Spring 2004 5 Logical Effort Introduction Example Slide 3 Delay in a Logic Gate Express delays in process independent unit d d abs 32 bits 5 Logical Effort 16 Register File CMOS VLSI Design Slide 4 Delay in a Logic Gate Express delays in process independent unit 3RC A 3 0 A 3 0 16 words CMOS VLSI Design Ben Bitdiddle is the memory designer for the Motoroil 68W86 an embedded automotive processor Help Ben design the decoder for a register file Decoder specifications 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit sized transistors True and complementary address inputs A 3 0 Each input may drive 10 unit sized transistors Ben needs to decide How many stages to use How large should each gate be How fast can decoder operate Logical effort is a method to make these decisions Uses a simple model of delay Allows back of the envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries 5 Logical Effort Slide 2 4 16 Decoder Chip designers face a bewildering array of choices What is the best circuit topology for a function How many stages of logic give least delay How wide should the transistors be CMOS VLSI Design 12 ps in 180 nm process 40 ps in 0 6 m process d d abs Delay has two components d f p 5 Logical Effort CMOS VLSI Design Slide 5 5 Logical Effort CMOS VLSI Design Slide 6 1 Delay in a Logic Gate Express delays in process independent unit Express delays in process independent unit d abs d Delay has two components Delay has two components d f p d f p Effort delay f gh a k a stage effort Again has two components 5 Logical Effort Effort delay f gh a k a stage effort Again has two components g logical effort Measures relative ability of gate to deliver current g 1 for inverter CMOS VLSI Design Slide 7 Delay in a Logic Gate Express delays in process independent unit d d abs 5 Logical Effort CMOS VLSI Design Slide 8 Delay in a Logic Gate Express delays in process independent unit d abs d Delay has two components d abs Delay has two components d f p d f p Effort delay f gh a k a stage effort Again has two components h electrical effort Cout Cin Ratio of output to input capacitance Sometimes called fanout 5 Logical Effort Parasitic delay p Represents delay of gate driving no load Set by internal parasitic capacitance CMOS VLSI Design Slide 9 5 Logical Effort Delay Plots d f p gh p 2 input NAND NormalizedDelay d 6 d f p gh p Inverter g p d g p d 3 Slide 10 Delay Plots 5 4 CMOS VLSI Design What about NOR2 2 1 2 input NAND 6 NormalizedDelay d d Delay in a Logic Gate Inverter 5 3 g 1 p 1 d h 1 2 EffortDelay f 4 g 4 3 p 2 d 4 3 h 2 1 Parasitic Delay p 0 0 0 1 2 3 4 5 0 ElectricalEffort h Cout Cin 5 Logical Effort CMOS VLSI Design 1 2 3 4 5 ElectricalEffort h Cout Cin Slide 11 5 Logical Effort CMOS VLSI Design Slide 12 2 Computing Logical Effort DEF Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs fanout plots Or estimate by counting transistor widths 2 A 2 Y 2 Y 1 A 2 B 2 Cin 3 g 3 3 A 4 B 4 Y 1 Gate type Cin 4 g 4 3 2 3 4 n NAND 4 3 5 3 6 3 n 2 3 NOR 5 3 7 3 9 3 2n 1 3 2 2 2 2 4 4 6 12 6 8 16 16 8 Inverter 1 2 XOR XNOR Cin 5 g 5 3 CMOS VLSI Design Slide 13 5 Logical Effort CMOS VLSI Design Slide 14 Example Ring Oscillator Parasitic delay of common gates In multiples of pinv 1 Gate type Number of inputs 1 1 Catalog of Gates Estimate the frequency of an N stage ring oscillator Number of inputs 1 2 3 4 n 2 3 4 n 2 3 4 n 4 6 8 2n 4 6 8 1 NAND NOR Tristate mux Logical effort of common gates Tristate mux 5 Logical Effort Inverter Catalog of Gates 2 XOR XNOR 5 Logical Effort CMOS VLSI Design Logical Effort Electrical Effort Parasitic Delay Stage Delay Frequency Slide 15 Example Ring Oscillator Estimate the frequency of an N stage ring oscillator 5 Logical Effort g h p d fosc CMOS VLSI Design Slide 16 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter d Logical Effort Electrical Effort Parasitic Delay Stage Delay Frequency 5 Logical Effort 31 stage ring oscillator in g 1 0 6 m process has h 1 frequency of 200 MHz p 1 d 2 fosc 1 2 N d 1 4N CMOS VLSI Design Slide 17 Logical Effort Electrical Effort Parasitic Delay Stage Delay 5 Logical Effort g h p d CMOS VLSI Design Slide 18 3 Example FO4 Inverter Estimate the delay of a fanout of 4 FO4 inverter d Logical Effort Electrical Effort Parasitic Delay Stage Delay g 1 h 4 p 1 d 5 Logical effort generalizes to multistage networks Path Logical Effort G gi 200 ps in 0 6 m process H Path Effort F f i gi hi 10 g1 1 h1 x 10 Slide 19 Logical effort generalizes to multistage networks Path Logical Effort G gi Cout path Cin path CMOS VLSI Design Slide 21 GH 1 5 90 5 18 18 15 15 5 6 90 15 6 g1g2h1h2 36 2GH 5 Logical Effort CMOS VLSI Design 15 CMOS VLSI Design 90 Slide 22 Introduce branching effort Accounts for branching between stages in path 90 b 15 90 Branching Effort No Consider paths that branch G H GH h1 h2 F Slide 20 5 5 Logical Effort Paths that Branch 15 CMOS VLSI Design 15 Can we write F GH 5 Logical Effort 20 Paths that Branch G H GH h1 h2 F F f i gi hi Path Effort z g4 1 h4 20 z No Consider paths that branch H Cin path y g3 4 3 h3 z y g2 5 3 h2 y x 5 Logical Effort Multistage Logic Networks Path Electrical Effort x 60 ps in a 180 nm process CMOS VLSI Design Cout path Path Electrical Effort The FO4 delay is about f 3 ns in an f m process 5 Logical Effort Multistage Logic Networks 90 Con path Coff path Con path B bi Note h i BH Now we compute the path effort F GBH Slide 23 5 Logical Effort CMOS VLSI Design Slide …