Final Assembly Your final project chip consists of a core and a pad ring Core is the guts Pad ring or pad frame connects the guts to the outside world It s critical to do a functional simulation of your whole chip including the pads Make sure you can drive the chip from the external interface Make sure you have the core connected to the pads correctly Core Sizes All things are in terms of Tiny Chip Units TCUs 1 TCU 1 5x1 5mm outside dimension 1 TCU 900x900 usable core area 2 TCU 900x2300 usable core area 4 TCU 2300x2300 usable core area More on this later Core The guts of your chip Chip Core The Chip Core is everything that is inside the Pad Ring Try to floorplan your core so that it s as small a rectangle as possible At the very least make sure it fits in the frame you ve chosen Make sure to connect vdd and gnd in the core This core can be DRC and LVS checked This core can be simulated for functionality This core is then routed to the pads Connecting Core to Pads Once your core is complete you need to connect it to the pad frame Then you re do the functional simulation but through the pads this time You should be able to re use your testfixture Also a final DRC and LVS which includes the pads Use vcar for connecting the core to the pads Chapter 12 in the CAD manual Pad Ring The connection to the outside world 1 The Connected Chip Tutorial Example A tiny state machine in a 1 tiny chip frame Pad Cells Driving Large Capacitances Started with a set of pads from MOSIS Originally from Tanner Tools pads Problem the pads don t DRC LVS or simulate Cameron Charles re did the cells in 2002 as a grad student to fix these issues Result is UofU Pads uusoc facility cad common local Cadence lib OA UofU Pads Use library manager to add this library Name it UofU Pads They now DRC LVS and simulate Using Cascaded Buffers How to Design Large Transistors 2 Tristate Buffers Bonding Pad Design Bonding Pad GND 100 m Out VDD UofU Pads In GND Out UofU Pads 255u Tanner Pads prototype of UofU Pads UofU Pads 3 UofU Pads ESD and Analog Pads ESD Protection Pads from MOSIS ASIC Pads UofU Pads pad bidirhe Bidirectional pad with high enable pad in Digital input pad pad out Digital output pad pad vdd pad gnd Power supply pads pad io pad io nores Analog pads with and without series resistor pad nc pad space Non connecting pad and spacer 4 Pad Interfaces pad bidirhe pad bidirhe pad bidirhe EN DataOut DataIn DataInB pad DataOut drives a 78 p x 45 n inverter 30x Which then drives a 200 p x 200 n output driver 133x DataIn and DataInB come from 96 p x 54 n inverters 36x EN drives a 16 p x 9 n inverter 6x All signal pads are built from this one All signals on are M2 pad bidirhe Moderately complex pullup pulldown structure pad bidirhe Look at just the metal layers EN DataOut DataInB DataIn is the order M2 connections for EN DataOut DataIn DataInB UofU Pads Middle connection is direct connection to the pad don t use it You put metal2 shape pins over the connection points for icc pad out pad out pad out pad DataOut pad in pad in DataIn DataInB pad Like pad bidirhe but with EN already tied high for you All you need to connect is DataOut 5 pad out pad out You connect your signal to the DataOut connection into 78 p x 45 n inv 30x You connect your signal to the DataOut connection into 78 p x 45 n inv 30x pad in pad in Like pad bidirhe but with EN tied low already for you Connect to the DataInB and DataIn port Power Supply Pads DataIn and DataInB provide input signals Driven from 94 p x 54 n inverters 36x pad vdd pad vdd pad vdd pad gnd pad gnd Vdd is on a big fat metal1 line 28 8u wide 6 pad gnd More Pads GND is also on a big fat metal1 line Also 28 8u Timetable Available Frames Final Chip Assembly Due Wednesday December 14th Take the pad cells and make a pad ring Connect your working core to the pad ring Remember that Tiny Chip Units are 1 5mm X 1 5mm and are not divisible A 3 1mm X 2 8mm chip would cost 6 TCUs Preference will go to the well simulated chips Secondary preference will be for the smaller well simulated chips Frame1 38 Frame1 38 Frame2h 70 Frame2v 70 Frame4 78 Frame4 80 1 2 4 indicate how many Tiny Chip Units h and v indicate horizontal and vertical for the rectangular core frames indicates how many signal pins are available Vdd and gnd are in the right spots DON T MOVE THEM Frame1 38 40 pins total 38 signal pins 10 on each side 40 pins total 38 signal pins 10 on each side 990 x 990 core 990 x 990 core Save room for Routing to pads 900 x 900 Usable core Save room for Routing to pads 900 x 900 Usable core 7 Frame1 38 Example Frame1 Chip 40 pins total 38 signal pins 10 on each side 990 x 990 core Save room for Routing to pads 900 x 900 Usable core Example Frame1 Chip Frame2h 68 72 pins total 70 signal pins 990 x 2430 core 900 x 2300 usable Frame2h 68 Frame4 78 72 pins total 68 signal pins 990 x 2430 core 900 x 2300 usable 84 total pins 78 signal pins 2490 x 2490 2300 x 2300 usable 8 Frame4 78 How to Use the Rings Copy the pad ring of your choice uusoc facility cad common local Cadence lib OA UofU Pads From UofU Pads To your project directory 84 total pins 78 signal pins 2490 x 2490 2300 x 2300 usable Leave the pad vdd and pad gnd where they are Select other pads use properties to change to the pad type you want DON T move them Use pad bidirhe pad out and pad in Frame Schematic Frame layout Frame1 38 with the right pads for the drink machine Frame1 38 with the right pads for the drink machine Pins Pins Frame1 38 with the right pads for the drink machine Frame1 38 with the right pads for the drink machine 9 Frame symbol Frame1 38 with the right pads for the drink machine Layout with Virtuoso XL Do placement and connect vdd and gnd Vdd Connections Notice how the pad frame is connected Connect to Core Use this to start the ccar routing process Connect with icc Let ccar the routing Gnd Connections Notice how the pad frame is connected 10 Now Simulate the Whole Chip Use essentially the same testbench that you used for the core This time you ll be simulating with the pads in place You ll need to place one more …