Verilog sim Synthesis and Place Route CS ECE 6710 Tool Suite Synopsys Design Compiler Behavioral Verilog Synopsys design compiler Cadence Encounter Digital Implementation System EDI Your Library Structural Verilog Cadence EDI Circuit Layout CCAR AutoRouter Design Compiler Synthesis of behavioral to structural Three ways to go 1 Type commands to the design compiler shell 2 3 Start with syn dc and start typing Write a script Use syn script tcl as a starting point Use the Design Vision GUI Friendly menus and graphics 4 Compile the design compile or compile ultra Does the actual synthesis 5 Write out the results Make sure to change names Write out structural verilog report ddc sdc files LVS Layout XL Cadence Composer Schematic Design Compiler Basic Flow 1 Define environment target libraries your cell library synthetic libraries DesignWare libraries link libraries libraries to link against 2 Read in your structural Verilog Usually split into analyze and elaborate 3 Set constraints Design Compiler Basic Flow Cadence Virtuoso Layout Verilog sim timing define clock loads etc beh2str the simplest script beh2str script set target library list getenv LIBFILE set link library concat concat target library synthetic library read file f verilog getenv INFILE This command will fix the problem of having assign statements left in your structural file set fix multiple port nets all buffer constants compile ungroup all check design always do change names before write redirect change names change names rules verilog hierarchy verbose write f verilog output getenv OUTFILE quit 1 synopsys dc setup set SynopsysInstall getenv SYNOPSYS set search path list format s s SynopsysInstall libraries syn format s s SynopsysInstall dw sim ver define design lib WORK path WORK set synthetic library list dw foundation sldb set synlib wait for design license list DesignWare Foundation set link library concat concat target library synthetic library set symbol library list generic sdb syn script tcl uusoc facility cad common local class 6710 F11 synopsys search path should include directories with memory db files as well as the standard cells set search path list format s s SynopsysInstall libraries syn format s s SynopsysInstall dw sim ver your library path goes here target library list should include all target db files set target library list your library name db synthetic library is set in synopsys dc setup to be the dw foundation library set link library concat concat target library synthetic library syn script tcl Timing and loading information set myPeriod ns 10 desired clock period sets speed goal set myInDelay ns 0 25 delay from clock to inputs valid set myOutDelay ns 0 25 delay from clock to output valid set myInputBuf INVX4 name of cell driving the inputs set myLoadLibrary Lib name of library the cell comes from set myLoadPin A pin that outputs drive What beh2str leaves out Timing No clock defined so no target speed No input drive defined so assume infinite drive No output load define so assume something syn script tcl below are parameters that you will want to set for each design list of all HDL files in the design set myFiles list all your structural Verilog files set fileFormat verilog verilog or VHDL set basename basename Name of top level module set myClk clk The name of your clock set virtual 0 1 if virtual clock 0 if real clock compiler switches set useUltra 1 1 for compile ultra 0 for compile mapEffort useUngroup are for non ultra compile set mapEffort1 medium First pass low medium or high set mapEffort2 medium second pass low medium or high set useUngroup 1 0 if no flatten 1 if flatten syn script tcl the following control which output files you want They should be set to 1 if you want the file 0 if not set write v 1 compiled structural Verilog file set write ddc 0 compiled file in ddc format set write sdf 0 sdf file for back annotated timing sim set write sdc 1 sdc constraint file for place and route set write rep 1 report file from compilation set write pow 0 report file for power estimate Control the writing of result files set runname struct Name appended to output files 2 syn script tcl analyze and elaborate the files analyze format fileFormat lib WORK myfiles elaborate basename lib WORK update current design basename The link command makes sure that all the required design parts are linked together The uniquify command makes unique copies of replicated modules link uniquify now you can create clocks for the design if virtual 0 create clock period myPeriod ns myClk else create clock period myPeriod ns name myClk syn script tcl Set the driving cell for all inputs except the clock The clock has infinite drive by default This is usually what you want for synthesis because you will use other tools like SOC Encounter to build the clock tree or define it by hand set driving cell library myLoadLibrary lib cell myInputBuf remove from collection all inputs myClk set the input and output delay relative to myclk set input delay myInDelay ns clock myClk remove from collection all inputs myClk set output delay myOutDelay ns clock myClk all outputs set the load of the circuit outputs in terms of the load of the next cell that they will drive also try to fix hold time issues set load load of format s s s s s myLoadLibrary myInputBuf myLoadPin all outputs set fix hold myClk syn script tcl now compile the design with given mapping effort and do a second compile with incremental mapping or use the compile ultra meta command if useUltra 1 compile ultra else if useUngroup 1 compile ungoup all map effort mapEffort1 compile incremental mapping map effort mapEffort2 else compile map effort mapEffort1 compile incremental mapping map effort mapEffort2 syn script tcl Check things for errors check design report constraint all violators set filebase format s s s basename runname structural synthesized file as verilog if write v 1 set filename format s s filebase v redirect change names change names rules verilog hierarchy verbose write format verilog hierarchy output filename write the rest of the desired files then quit Using Scripts Modify syn script tcl or write your own syn dc f scriptname tcl Make sure to check output Using Design Vision You can do all of these commands from the design vision gui if you like syn dv Follow the same steps as the script Set libraries in your own synopsys dc setup analyze elaborate define clock and set constraints compile write out results 3 Setup analyze elaborate File Analyze File