Where are we Subsystem Design Registers and Register Files Adders and ALUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath Data Path Design Block diagram style data path description 1 Bit Slice Design Control Bit 2 Bit 1 Data Out Multiplexer Shifter Adder Register Data In Bit 3 Bit 0 Tile identical processing elements Layout Reality Bit Slice Design Control Bit 2 Bit 1 Data Out Multiplexer Shifter Adder Register Data In Bit 3 Bit 0 Tile identical processing elements Layout Reality 2 Bit Slice Plan Recall planning a DFF to make a register Inputs on top in M2 Outputs on bottom in M2 Clock and Clock bar routed horizontally in M1 D2 D0 D1 Qb2 Q2 Qb1 Q1 Vdd C Cb Q0 Vss Qb0 Bit Slice Plan Now extend this to a register file D inputs go to all cells Can select one register for writing by controlling the clock Q outputs go all the way through the register file Each cell can drive Q from enabled inverter Now you can select one register for reading by selecting which cell is driving its output D2 D1 D0 C Cb En C Cb En Q2 Q1 Q0 3 C Cb En C Cb En C Cb En C Cb En Bit Slice Plan Q0 D0 Q1 D1 Q2 D2 Bit Slice Design Control Bit 2 Bit 1 Data Out Multiplexer Shifter Adder Register Data In Bit 3 Bit 0 Tile identical processing elements 4 Multi Port Register Re1 Re0 Multi Port Register 5 Bit Slice Design Control Bit 2 Bit 1 Data Out Multiplexer Shifter Adder Register Data In Bit 3 Bit 0 Tile identical processing elements Where are power lines Bit Slice Design Control Bit 2 Bit 1 Data Out Multiplexer Shifter Adder Register Data In Bit 3 Bit 0 Tile identical processing elements Where are power lines Basic Comb scheme 6 Chip Wide View of Power Power Routing is a global chipwide issue Here s another approach Note the Vdd and Gnd pads Global rings with combs for regions of the chip Chip Wide View of Power Power Routing is a global chipwide issue Here s another approach Note the Vdd and Gnd pads Global rings with combs for regions of the chip 7 Core power routing Core power routing 8 Chip Wide View of Power Another view of the same issue Watch out for routing blockages A Tweak on the Scheme Same basic scheme But with no internal jumpers Jumpers are restricted to outer loops 9 Adders Etc Check out Chapter 10 in your text Basic Addition Full Adder A Cin B Full adder Cout Sum kill kill 10 Boolean Equations A Cin B Full adder Cout Sum A Direct Implementation Fig 10 3 in your text 32 transistors 11 Use the Factored Equations VD D V DD Ci A B A B A B Ci A B V DD X Ci Ci A S Ci A B B V DD A B A Ci Co B 28 Transistors Fully static complex gate implementation Getting Rid of Inverters Even C ell A0 C i 0 F A S0 A1 B0 C o 0 B1 FA S1 A2 C o 1 A3 B2 FA O dd C ell C o 2 S2 B3 FA C o 3 S3 E x plo it Inv ers io n P rop erty N ote need 2 different typ es of cells Can improve performance by removing inverters from carry chain 12 A Better Static Gate Combine gates and reuse subterms A Better Static Gate Sometimes called a mirror adder 13 Mirror Adder Considerations Feed the Carry In to the inner inputs so the internal capacitance is already discharged Make all transistors whose gates are connected to Cin and carry logic minimum size minimizes branching effort on critical path carry out Determine gate widths by Logical Effort reduce effort from C to CoutB at the expense of Sum Use relatively large transistors on critical path so that stray wiring cap is a small fraction of overall cap Adder Layout Examples from Weste and Eshraghian Standard Cell vs Datapath Definitely worth looking at carefully 14 Datapath Layout A little tricky to figure out You may not want to use this exact layout but it might give you ideas Start by identifying vdd and gnd paths Think about rotating it counter clock wise Think about a taller circuit that matches the bit pitch of your register Datapath Layout 15 Example Datapath Layout Addition and Subtraction Remember back to your logic design class Add the two s complement to subtract Take two s complement by inverting all the bits and adding one Use the carry in to add one A B Out Use an XOR to invert or not 0 0 0 0 1 1 1 0 1 1 1 0 16 Two s Complement Add Sub Aside XOR Gates Slightly tricky gate AB A B Lots of different schematics 17 Another XOR gate Not too bad if you already have A A B B floating around If not you ll need a couple inverters too B A B A A B A B XOR B A B A A B A B XNOR Yet Another XOR Gate DCVSL section 6 2 3 in your text Differential Cascode Voltage Switch Logic Make sure that the combinational pull down networks are complementary Out Differential Inputs Out PDN1 PDN2 18 DCVSL XOR XNOR Out Out B B B B A A Generates both XOR XNOR Still static but might be slower than others Another DCVSL Example Out Out D E A B C D E B A C Pull down stacks must be complementary 19 DCVSL Large XOR Four input XOR aka odd parity Out Out D D D D C C C C B B B B A A DCVSL Large XOR Four input XOR aka odd parity Out Out D D D D C C C C B B B B A A 20 DCVSL Large XOR Four input XOR aka odd parity Out Out D D D D C C C C B B B B A A Transmission Gate XOR Tiny clever circuit If A is high N1 P1 act like inverter If A is low B is passed to the output through transmission gate 21 Transmission Gate Adder Another Version P VDD A P A A P B VDD Ci A P Ci VDD Ci S Sum Generation Ci P B VDD A P Co Carry Generation Ci A Setup P 22 Yet Another Version An Example Layout Not the same style we re used to seeing 23 More Pass Transistors Complementary Pass Transistor Logic CPL Slightly faster but more area B B B C B C B C B C A S B C B C B C B C Cout A A S A Cout B B Speeding Up Addition It all comes back to the carry circuit Ripple carry delay goes from low order to high order bit This determines the speed of the addition Many many ways to speed up the carry calculation Section 10 2 2 in your text …