1Introduction toCMOS VLSIDesignLecture 2: MIPS Processor ExampleDavid HarrisHarvey Mudd CollegeSpring 20042: MIPS Processor Example Slide 2CMOS VLSI DesignOutline Design Partitioning MIPS Processor Example– Architecture– Microarchitecture– Logic Design– Circuit Design– Physical Design Fabrication, Packaging, Testing22: MIPS Processor Example Slide 3CMOS VLSI DesignActivity 2 Sketch a stick diagram for a 4-input NOR gate2: MIPS Processor Example Slide 4CMOS VLSI DesignActivity 2 Sketch a stick diagram for a 4-input NOR gateAVDDGNDBCYD32: MIPS Processor Example Slide 5CMOS VLSI DesignCoping with Complexity How to design System-on-Chip?– Many millions (soon billions!) of transistors– Tens to hundreds of engineers Structured Design Design Partitioning2: MIPS Processor Example Slide 6CMOS VLSI DesignStructured Design Hierarchy: Divide and Conquer– Recursively system into modules Regularity– Reuse modules wherever possible– Ex: Standard cell library Modularity: well-formed interfaces– Allows modules to be treated as black boxes Locality– Physical and temporal42: MIPS Processor Example Slide 7CMOS VLSI DesignDesign Partitioning Architecture: User’s perspective, what does it do?– Instruction set, registers– MIPS, x86, Alpha, PIC, ARM, … Microarchitecture– Single cycle, multcycle, pipelined, superscalar? Logic: how are functional blocks constructed– Ripple carry, carry lookahead, carry select adders Circuit: how are transistors used– Complementary CMOS, pass transistors, domino Physical: chip layout– Datapaths, memories, random logic2: MIPS Processor Example Slide 8CMOS VLSI DesignGajski Y-Chart52: MIPS Processor Example Slide 9CMOS VLSI DesignMIPS Architecture Example: subset of MIPS processor architecture– Drawn from Patterson & Hennessy MIPS is a 32-bit architecture with 32 registers– Consider 8-bit subset using 8-bit datapath– Only implement 8 registers ($0 - $7)– $0 hardwired to 00000000– 8-bit program counter2: MIPS Processor Example Slide 10CMOS VLSI DesignInstruction Set62: MIPS Processor Example Slide 11CMOS VLSI DesignInstruction Encoding 32-bit instruction encoding– Requires four cycles to fetch on 8-bit datapathformat example encodingRIJ0 ra rb rd 0 functopopra rb imm6666555555 1626add $rd, $ra, $rbbeq $ra, $rb, immj dest dest2: MIPS Processor Example Slide 12CMOS VLSI DesignFibonacci (C)f0= 1; f-1= -1fn= fn-1+ fn-2f = 1, 1, 2, 3, 5, 8, 13, …72: MIPS Processor Example Slide 13CMOS VLSI DesignFibonacci (Assembly) 1ststatement: n = 8 How do we translate this to assembly?2: MIPS Processor Example Slide 14CMOS VLSI DesignFibonacci (Assembly)82: MIPS Processor Example Slide 15CMOS VLSI DesignFibonacci (Binary) 1ststatement: addi $3, $0, 8 How do we translate this to machine language?– Hint: use instruction encodings belowformat example encodingRIJ0 ra rb rd 0 functopopra rb imm6666555555 1626add $rd, $ra, $rbbeq $ra, $rb, immj dest dest2: MIPS Processor Example Slide 16CMOS VLSI DesignFibonacci (Binary) Machine language program92: MIPS Processor Example Slide 17CMOS VLSI DesignMIPS Microarchitecture Multicycle µarchitecture from Patterson & HennessyPCMux01RegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2Instruction[15: 11]Mux01Mux011Instruction[7: 0]Instruction[25: 21]Instruction[20: 16]Instruction[15 : 0]InstructionregisterALUcontrolALUresultALUZeroMemorydataregisterABIorDMemReadMemWriteMemtoRegPCWriteCondPCWriteIRWrite[3:0]ALUOpALUSrcBALUSrcARegDstPCSourceRegWriteControlOutputsOp[5: 0]Instruction[31:26]Instruction [5 : 0]Mux02JumpaddressInstruction [5: 0]6 8Shiftleft 211Mux032Mux01ALUOutMemoryMemDataWritedataAddressPCEnALUControl2: MIPS Processor Example Slide 18CMOS VLSI DesignMulticycle ControllerPCWritePCSource = 10ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCondPCSource = 01ALUSrcA =1ALUSrcB = 00ALUOp= 10RegDst = 1RegWriteMemtoReg = 0MemWriteIorD = 1MemReadIorD = 1ALUSrcA = 1ALUSrcB = 10ALUOp = 00RegDst=0RegWriteMemtoReg=1ALUSrcA = 0ALUSrcB = 11ALUOp = 00MemReadALUSrcA = 0IorD = 0IRWrite3ALUSrcB = 01ALUOp = 00PCWritePCSource = 00Instruction fetchInstruction decode/register fetchJumpcompletionBranchcompletionExecutionMemory addresscomputationMemoryaccessMemoryaccessR-type completionWrite-back step(Op='LB')or(Op='SB')(Op=R-type)(Op='BEQ')(Op = 'J')(Op='SB')(Op = 'L B')7041211951086ResetMemReadALUSrcA = 0IorD = 0IRWrite2ALUSrcB = 01ALUOp = 00PCWritePCSource = 001MemReadALUSrcA = 0IorD = 0IRWrite1ALUSrcB = 01ALUOp = 00PCWritePCSource = 002MemReadALUSrcA = 0IorD = 0IRWrite0ALUSrcB = 01ALUOp = 00PCWritePCSource = 003102: MIPS Processor Example Slide 19CMOS VLSI DesignLogic Design Start at top level– Hierarchically decompose MIPS into units Top-level interfaceresetph1ph2crystaloscillator2-phaseclockgeneratorMIPSprocessoradrwritedatamemdataexternalmemorymemreadmemwrite8882: MIPS Processor Example Slide 20CMOS VLSI DesignBlock Diagramdatapathcontrolleralucontrolph1ph2resetmemdata[7:0]writedata[7:0]adr[7:0]memreadmemwriteop[5:0]zeropcenregwriteirwrite[3:0]memtoregiordpcsource[1:0]alusrcb[1:0]alusrcaaluop[1:0]regdstfunct[5:0]alucontrol[2:0]PCMux01RegistersWriteregisterWritedataReaddata 1Readdata 2Readregister1Readregister2Instru cti on[15:11]Mux01Mux011Instruction[7: 0]Instru cti on[25: 21]Instru cti on[20: 16]Instru cti on[15: 0]InstructionregisterALUcontrolALUresultALUZeroMemorydataregisterABIorDMemReadMemWriteMemtoRegPCWriteCondPCWriteIRWrite[3:0]ALUOpALUSrcBALUSrcARegDstPCSourceRegWriteControlOutputsOp[5:0 ]Instruction[31:26]Instruction[5: 0]Mux02JumpaddressInstruction[5:0]6 8Shiftleft211Mux032Mux01ALUOutMemoryMemDataWritedataAddressPCEnALUControl112: MIPS Processor Example Slide 21CMOS VLSI DesignHierarchical Designmipscontrolleralucontroldatapathstandardcell librarybitslicezipperaluand2flopinv4xmux2mux4ramslicefulladdernand2nor2or2invtri2: MIPS Processor Example Slide 22CMOS VLSI DesignHDLs Hardware Description Languages– Widely used in logic design– Verilog and VHDL Describe hardware using code– Document logic functions– Simulate logic before building– Synthesize code into gates and layout• Requires a library of standard cells122: MIPS Processor Example Slide 23CMOS VLSI DesignVerilog Examplemodule fulladder(input a, b, c, output s, cout);sum s1(a, b, c, s);carry c1(a, b, c, cout);endmodulemodule carry(input a, b, c, output cout)assign cout = (a&b) | (a&c) | (b&c);endmoduleabcscout