Introduction to CMOS VLSI Design Lecture 2 MIPS Processor Example David Harris Harvey Mudd College Spring 2004 Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design Circuit Design Physical Design Fabrication Packaging Testing 2 MIPS Processor Example CMOS VLSI Design Slide 2 1 Activity 2 Sketch a stick diagram for a 4 input NOR gate 2 MIPS Processor Example CMOS VLSI Design Slide 3 Activity 2 Sketch a stick diagram for a 4 input NOR gate VDD A B C D Y GND 2 MIPS Processor Example CMOS VLSI Design Slide 4 2 Coping with Complexity How to design System on Chip Many millions soon billions of transistors Tens to hundreds of engineers Structured Design Design Partitioning 2 MIPS Processor Example CMOS VLSI Design Slide 5 Structured Design Hierarchy Divide and Conquer Recursively system into modules Regularity Reuse modules wherever possible Ex Standard cell library Modularity well formed interfaces Allows modules to be treated as black boxes Locality Physical and temporal 2 MIPS Processor Example CMOS VLSI Design Slide 6 3 Design Partitioning Architecture User s perspective what does it do Instruction set registers MIPS x86 Alpha PIC ARM Microarchitecture Single cycle multcycle pipelined superscalar Logic how are functional blocks constructed Ripple carry carry lookahead carry select adders Circuit how are transistors used Complementary CMOS pass transistors domino Physical chip layout Datapaths memories random logic 2 MIPS Processor Example CMOS VLSI Design Slide 7 Gajski Y Chart 2 MIPS Processor Example CMOS VLSI Design Slide 8 4 MIPS Architecture Example subset of MIPS processor architecture Drawn from Patterson Hennessy MIPS is a 32 bit architecture with 32 registers Consider 8 bit subset using 8 bit datapath Only implement 8 registers 0 7 0 hardwired to 00000000 8 bit program counter 2 MIPS Processor Example CMOS VLSI Design Slide 9 Instruction Set 2 MIPS Processor Example CMOS VLSI Design Slide 10 5 Instruction Encoding 32 bit instruction encoding Requires four cycles to fetch on 8 bit datapath format example encoding 6 5 5 5 5 6 ra rb rd 0 funct R add rd ra rb 0 6 5 5 16 I beq ra rb imm op ra rb imm 6 26 J j dest op dest 2 MIPS Processor Example CMOS VLSI Design Slide 11 Fibonacci C f0 1 f 1 1 fn fn 1 fn 2 f 1 1 2 3 5 8 13 2 MIPS Processor Example CMOS VLSI Design Slide 12 6 Fibonacci Assembly 1st statement n 8 How do we translate this to assembly 2 MIPS Processor Example CMOS VLSI Design Slide 13 Fibonacci Assembly 2 MIPS Processor Example CMOS VLSI Design Slide 14 7 Fibonacci Binary 1st statement addi 3 0 8 How do we translate this to machine language Hint use instruction encodings below format example encoding 6 5 5 5 5 6 ra rb rd 0 funct R add rd ra rb 0 6 5 5 16 I beq ra rb imm op ra rb imm 6 26 J j dest op dest 2 MIPS Processor Example CMOS VLSI Design Slide 15 Fibonacci Binary Machine language program 2 MIPS Processor Example CMOS VLSI Design Slide 16 8 MIPS Microarchitecture Multicycle architecture from Patterson Hennessy PCWriteCond PCEn PCSource PCWrite Outputs ALUOp IorD ALUSrcB MemRead MemWrite ALUSrcA Control RegWrite MemtoReg IRWrite 3 0 Op 5 0 RegDst 0 M 6 Instruction 5 0 PC 0 M u x 1 Shift left 2 8 1 u Jump address x 2 Instruction 31 26 Address Memory MemData Instruction 25 21 Read register 1 Instruction 20 16 Read Read register 2 data 1 Registers Write Read register data 2 0 M Instruction u x 15 11 1 Instruction 15 0 Write data Instruction register 0 M u x 1 A B 1 Write data 0 M u x 1 Instruction 7 0 Memory data register Zero ALU ALU result ALUOut 0 1 M u 2 x 3 ALU control ALUControl Instruction 5 0 2 MIPS Processor Example CMOS VLSI Design Slide 17 Multicycle Controller Instruction fetch Reset Memory address computation Op 5 L B p or O S B Execution 9 ALUSrcA 1 ALUSrcB 10 ALUOp 00 ype R t p O Branch completion 11 ALUSrcA 1 ALUSrcB 00 ALUOp 10 ALUSrcA 1 ALUSrcB 00 ALUOp 01 PCWriteCond PCSource 01 4 ALUSrcA 0 ALUSrcB 11 ALUOp 00 Jump completion 12 PCWrite PCSource 10 O p S B Op L B Instruction decode register fetch MemRead ALUSrcA 0 IorD 0 IRWrite0 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 B EQ 3 MemRead ALUSrcA 0 IorD 0 IRWrite1 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 2 MemRead ALUSrcA 0 IorD 0 IRWrite2 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 Op J 1 MemRead ALUSrcA 0 IorD 0 IRWrite3 ALUSrcB 01 ALUOp 00 PCWrite PCSource 00 O p 0 Memory access 6 Memory access 8 MemRead IorD 1 R type completion 10 MemWrite IorD 1 RegDst 1 RegWrite MemtoReg 0 Write back step 7 RegDst 0 RegWrite MemtoReg 1 2 MIPS Processor Example CMOS VLSI Design Slide 18 9 Logic Design Start at top level Hierarchically decompose MIPS into units Top level interface crystal oscillator 2 phase clock generator memread memwrite ph1 MIPS processor ph2 8 adr 8 memdata 2 MIPS Processor Example external memory 8 writedata reset CMOS VLSI Design Slide 19 Block Diagram PCWrit eCond PCEn PCSource PCWrite Outputs ALUOp IorD ALUSrcB MemRead MemWrite Control ALUSrcA RegWrite MemtoReg IRWrite 3 0 Op 5 0 RegDst 0 M 6 Instruction 5 0 PC memwrite 0 M u x 1 Shift left 2 8 Jump address 1 u x 2 Instruction 31 26 Instruction 25 21 Address Memory MemData Write data Instruction 15 0 Instruction register Instruction 7 0 Memory data register memread 0 M u x 1 Read register 1 Instruction 20 16 0 M Instruction u x 15 11 1 Read Read register 2 data 1 Registers Write Read register data 2 A B 1 Write data 0 M u x 1 Zero ALU ALU result ALUOut 0 1 M u 2 x 3 ALU control ALUControl Instruction 5 0 controller aluop 1 0 alucontrol alucontrol 2 0 funct 5 0 irwrite 3 0 regwrite iord regdst memtoreg pcsource 1 0 pcen alusrcb 1 0 alusrca zero op 5 0 ph1 ph2 reset adr 7 0 datapath writedata 7 0 memdata 7 0 2 MIPS Processor Example CMOS VLSI Design Slide 20 10 Hierarchical Design mips controller alucontrol datapath standard cell library bitslice inv4x flop ramslice alu fulladder or2 zipper and2 mux4 nor2 inv nand2 mux2 tri 2 MIPS Processor Example CMOS VLSI Design Slide 21 HDLs Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code into gates and layout Requires a library of standard cells 2 MIPS Processor Example CMOS VLSI Design Slide 22 11 Verilog Example module fulladder input a b c output s cout a b c a b cout sum carry endmodule s1 a b c s c1 a b c cout c carry sum s fulladder cout s module carry input a b c output cout assign cout a b a c b c endmodule 2 MIPS Processor