Testbench Template Testbench template generated by Cadence The Big Picture 1010010100100 1001000010100 1110101001110 1010100010011 0100100010001 DUT Device Under Test Actual Output Vectors Input Vector Table Pass Fail Display Compare Expected Output Vector Table Testing with the LV 500 Tektronix LV 500 Built in 1989 1991 I e Ancient technology eBay is a good source for spare parts these days Specifically designed to be a stand alone tester for ASICs I e More testing features than a basic logic analyzer Flavors of LV500s Common Features Test speeds up to 50MHz Up to 64 000 unique test vectors Network connection for uploading tests Thinlan ethernet 8 Meg of RAM 21 or 43 Meg hard drive 5 25 floppy 1 2M floppy 11010100101010 11110101010101 00101001010100 10010100010101 01010010010101 Expected Output Vectors What s an ASIC Tester Ours is built on a Tektronix DAS 9200 logic analyzer platform The main differences are in the test head the pattern error cards and the Schmoo The test head has up to 256 bi directional pins where each pin has programmable electronics voltage drive current drive voltage sense etc The pattern error cards store and compare the test vectors at up to 50MHz fast for 1989 A Schmoo lets you run repeated tests while the tester alters one or two independent variables like threshold delay cycle length voltage etc Flavors of LV500s LV514 192 test channels 12 sectors 160 are usable two sectors may be bad Pre wired test card for class chips should really be called LV513 but that s a long story LV512 128 test channels 8 sectors All channels are usable Used mostly for tutorial purposes But we have a new test card too 1 LV514 LV512 DUT Card 9 8 7 DUT Card Sectors Channels 6 5 A B 4 C 3 D 2 E F 0 1 Knowing What to Wire Bonding Chip Diagram A Bonding Diagram is a picture that shows how your chip was bonded to the chip frame It also shows how the chip frame is connected to the chip pins 2 Map Your Pins to Channels Pick tester sector channel assignments for each of your pins Signals that need the same voltage characteristics should be grouped in the same sector Each sector gets common voltage ranges More on this later Class DUT Card Pre wired for class chips 84 pin PGA with specific VDD and GND placements in the pad ring DUTmap txt on class web page http www eng utah edu cs6712 Signals that need the same timing should be grouped in the same quadrant Sectors 0 3 4 7 8 b c f are the four quadrants More on this later Wire things up Remember to keep a list of what you ve wired DUTmap txt Finished DUT Card PAD PIN TESTER CHANNEL MAP FOR CS EE 5710 DUT CARD Pad locations are taken from MOSIS bonding diagram PGA locations are taken from 84pin PGA bonding diagram Tester channels 6 7 8 9 A are used The notation is sector channel Vdd and GND connections are as per 5710 standard pad frame TESTER SIGNAL PAD PGA sec chn NAME no spaces 1 B02 6 C 2 C02 7 7 3 B01 6 B 4 C01 7 6 5 D02 7 D 6 D01 7 C 7 F02 GND GND 8 E02 8 1 9 E01 8 0 10 E03 8 7 12 F01 8 6 13 G01 8 A etc LV512 Boot Menu Now you have part 1 a wired DUT card that connects your chip to the tester On to part 2 configuring the tester LV500 Main Menu 3 LV500 Keyboard Layout Overview On every tester cycle the LV500 Applies a set of signals to the DUT The data to Force is defined in the Pattern Which signals are Forced on this cycle is defined in the template When the data are applied is defined relative to the clock phase template The names of the signals and which tester channels they are on are defined in the DUT wiring menu At the right time defined in the template the tester captures and compares the data from the DUT Compares against the data in the Pattern Procedure 1 Get your bonding diagram and map where your signals are on your chip 2 Decide how those pins will map to tester channels DUTmap txt 3 Decide on timing templates for all signals 4 Generate test vectors that include pin names templates and data vectors for every cycle 5 Put it all in a msa file Procedure 3 Procedure 2 6 Upload the msa file to the LV500 7 Convert the msa file to a tester setup file 8 Check all menus to make sure things are how you want them 1 2 3 4 5 Config DUT wiring Channel Template Pattern Tutorial DUT Card 9 Fix or modify test parameters 10 Run your test 11 Look at the results 1 Celebrate 2 Or diagnose and debug 3 Or decide to schmoo to get more info 4 Tutorial 1 74LS547 74LS547 3 to 8 decoder 547 DUT Wiring 547 Template 547 Pattern 547 Schmoo 5 Tutorial 2 74LS299 Shift Register shift L or R parallel load and output Bidirectional data bus 74LS299 Timing Control should be set up ahead of the clock Data should be sampled after the rising edge of the clock Data should be driven after the control is set up Avoid drive fights on bidirectional path 74LS299 Timing 74LS299 Shift Clear Template Cycle 200ns Control signals Delay 0ns Width 100ns Clock Delay 40ns Width 100ns Shift data Delay 20ns Width 80ns 74LS299 Load Template 74LS299 Pattern 6