Chapter 4 :: Hardware Description LanguagesChapter 4 :: TopicsIntroductionHDL to GatesVerilog ModulesBehavioral Verilog ExampleBehavioral Verilog SimulationBehavioral Verilog SynthesisVerilog SyntaxStructural Modeling - HierarchyBitwise OperatorsReduction OperatorsConditional AssignmentInternal VariablesPrecedenceNumbersBit Manipulations: Example 1Bit Manipulations: Example 2Z: Floating OutputDelaysSlide 21Sequential LogicAlways StatementD Flip-FlopResettable D Flip-FlopSlide 26D Flip-Flop with EnableLatchOther Behavioral StatementsCombinational Logic using alwaysCombinational Logic using caseSlide 32Combinational Logic using casezBlocking vs. Nonblocking AssignmentsRules for Signal AssignmentFinite State Machines (FSMs)FSM Example: Divide by 3FSM in VerilogParameterized ModulesTestbenchesExampleSlide 42Simple TestbenchSelf-checking TestbenchTestbench with TestvectorsSlide 46Testvectors FileTestbench: 1. Generate Clock2. Read Testvectors into Array3. Assign Inputs and Expected Outputs4. Compare Outputs with Expected OutputsSlide 52Copyright © 2007 Elsevier 4-<1>Chapter 4 :: Hardware Description LanguagesDigital Design and Computer Architecture David Money Harris and Sarah L. HarrisCopyright © 2007 Elsevier 4-<2>Chapter 4 :: Topics•Introduction•Combinational Logic•Structural Modeling•Sequential Logic•More Combinational Logic•Finite State Machines•Parameterized Modules•TestbenchesCopyright © 2007 Elsevier 4-<3>Introduction•Hardware description language (HDL): allows designer to specify logic function only. Then a computer-aided design (CAD) tool produces or synthesizes the optimized gates.•Most commercial designs built using HDLs•Two leading HDLs:–Verilog•developed in 1984 by Gateway Design Automation•became an IEEE standard (1364) in 1995–VHDL•Developed in 1981 by the Department of Defense•Became an IEEE standard (1076) in 1987Copyright © 2007 Elsevier 4-<4>HDL to Gates•Simulation–Input values are applied to the circuit–Outputs checked for correctness–Millions of dollars saved by debugging in simulation instead of hardware•Synthesis–Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them)IMPORTANT:When describing circuits using an HDL, it’s critical to think of the hardware the code should produce.Copyright © 2007 Elsevier 4-<5>Verilog ModulesTwo types of Modules:–Behavioral: describe what a module does–Structural: describe how a module is built from simpler modulesab ycVerilogModuleCopyright © 2007 Elsevier 4-<6>Behavioral Verilog Examplemodule example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;endmoduleVerilog:Copyright © 2007 Elsevier 4-<7>Behavioral Verilog Simulationmodule example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;endmoduleVerilog:Copyright © 2007 Elsevier 4-<8>Behavioral Verilog Synthesismodule example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;endmoduleSynthesis:Verilog:Copyright © 2007 Elsevier 4-<9>Verilog Syntax•Case sensitive–Example: reset and Reset are not the same signal.•No names that start with numbers –Example: 2mux is an invalid name.•Whitespace ignored•Comments:–// single line comment–/* multiline comment */Copyright © 2007 Elsevier 4-<10>Structural Modeling - Hierarchymodule and3(input a, b, c, output y); assign y = a & b & c;endmodulemodule inv(input a, output y); assign y = ~a;endmodulemodule nand3(input a, b, c output y); wire n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverterendmoduleCopyright © 2007 Elsevier 4-<11>Bitwise Operatorsmodule gates(input [3:0] a, b, output [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */ assign y1 = a & b; // AND assign y2 = a | b; // OR assign y3 = a ^ b; // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a | b); // NORendmodule// single line comment/*…*/ multiline commentCopyright © 2007 Elsevier 4-<12>Reduction Operatorsmodule and8(input [7:0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0];endmoduleCopyright © 2007 Elsevier 4-<13>Conditional Assignmentmodule mux2(input [3:0] d0, d1, input s, output [3:0] y); assign y = s ? d1 : d0; endmodule? : is also called a ternary operator because it operates on 3 inputs: s, d1, and d0.Copyright © 2007 Elsevier 4-<14>Internal Variablesmodule fulladder(input a, b, cin, output s, cout); wire p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin);endmodulepgsun1_coutcoutcoutscinbaCopyright © 2007 Elsevier 4-<15>Precedence~NOT*, /, % mult, div, mod+, - add,sub<<, >> shift<<<, >>> arithmetic shift<, <=, >, >= comparison==, != equal, not equal&, ~& AND, NAND^, ~^ XOR, XNOR|, ~| OR, XOR?:ternary operatorDefines the order of operationsHighestLowestCopyright © 2007 Elsevier 4-<16>NumbersNumber # Bits Base Decimal EquivalentStored3’b101 3 binary 5 101‘b11 unsized binary 3 00…00118’b11 8 binary 3 000000118’b1010_1011 8 binary 171 101010113’d6 3 decimal 6 1106’o42 6 octal 34 1000108’hAB 8 hexadecimal 171 1010101142 Unsized decimal 42 00…0101010Format: N'BvalueN = number of bits, B = baseN'B is optional but recommended (default is decimal)Copyright © 2007 Elsevier 4-<17>Bit Manipulations: Example 1assign y = {a[2:1], {3{b[0]}}, a[0], 6’b100_010};// if y is a 12-bit signal, the above statement produces:y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0// underscores (_) are used for formatting only to make it easier to read. Verilog ignores them.Copyright © 2007 Elsevier 4-<18>Bit Manipulations: Example 2module mux2_8(input [7:0] d0, d1, input s, output [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);endmodulemux2lsbmuxmux2msbmuxy[7:0][7:0]sd1[7:0][7:0]d0[7:0][7:0]s[3:0]d0[3:0][3:0]d1[3:0][3:0]y[3:0]s[7:4]d0[3:0][7:4]d1[3:0][7:4]y[3:0]Synthesis:Verilog:Copyright © 2007 Elsevier 4-<19>Z: Floating Outputmodule tristate(input [3:0] a, input