Lab 4 – A mini computer system designInstructor: C.-K. ChengNovember 23, 2005Agenda Administrative Due on 12/02 before discussion session 5% bonus on lab 4 if you submit on next Wednesday Today A more detailed system diagram How to design instruction memory using read-only memory (ROM) Interface signals using bus Instruction decoder (control block) using VHDL moduleSystem DiagramProgramCounterInstructionMemoryInstructionDecoderDatapathRegistersaddr[3:0]instr[6:4]instr[3:0]R1[3:0]result[3:0](to R3)OverflowCompareR2_enR1_enR3_enOVL_encomp_enR2[3:0]instr[3:2]R1_selProgram Counter Program counter (PC) is a memory address pointer. Implementation-wise, PC is nothing more than a binary counter. The instruction memory is designed to hold 16 instructions, hence the PC output is a 4-bit address addr[3:0], which cycles through 0 to 15.R2_enR1_enR3_enOVL_encomp_enR1_selInstructionMemory Instruction memory (IM) holds the binary encoding of the instructions. The size of IM is 16x7 16 instructions in total Each instruction is 7-bit wide To simply the implementation, we use read-only memery (ROM) to realize the IM.R2_enR1_enR3_enOVL_encomp_enR1_selInstructionDecoder Instruction Decoder (ID) generates the control signals for datapath and registers. ID is a bunch of combinational logic, and the most convenient way to design it is using VHDL module. R2_enR1_enR3_enOVL_encomp_enR1_selDatapath Datapath carries out the arithmetic operations. The operands are always from R1 and R2; the result is always stored in R3 except store command. Five arithmetic operations; use library components. Load/store Addition: ADD4 Shift: BRLSHFT4 Compare: COMPM4 Mask: bit-wise AND of the two operandsR2_enR1_enR3_enOVL_encomp_enR1_selRegisters Analysis of register usage Move: load memory to R1, R2 Add, shift, mask: produce result in R3 Store: load R3 to R1  Each register is enabled only when it’s needed.R2 R1R3MUXdpath_source[3:0]mem_source[3:0]R1_selR2[3:0]R1[3:0]R3[3:0]OVL_inComp_inComp_outOVL_outR2_enR1_enR3_enOVL_encomp_enR2_enR1_enR3_enOVL_encomp_enR1_selSuggestions Divide and conquer Design the whole architect and interface signals first, and then work down to individual modules. Sketch your design on paper before going to Xilinx.Instruction Memory Design Memory modules in Xilinx RAM (Random Access Memory): Writable ROM (Read-Only Memory) We will use ROM, hence the instructions are preloaded before the machine starts.IM Design II ROM16x1A0A1A2A3O0110101100001111INITThe data output (O) reflects the bit selected by the 4-bit address (A3 – A0). The ROM is initialized to a known value during configuration with the INIT=value parameter.IM Design III 16x7 memory blockIM Design IV 16x7 instruction memory initializationInitMove1 0100Move2 0110Add0 0 0 0 0 0 00 0 1 0 1 0 00 1 0 0 1 1 01 0 0 0 0 0 00 0 0 0 0 0 0instr 0instr 1instr 2instr 3instr 4~15Stored in a ROM16x1 module0000000200040008Content (hexadecimal)3210Id of the ROM16x1 module000060004500064Content (hexadecimal)Id of the ROM16x1 moduleIM Design V How to use bus in Xilinx Create a new schematic Before you place anything in the schematic, click Tools -> create I/O markersIM Design V You’ll see two I/O buses on the canvas Select the ROM16x1 module from the library and place multiple instances on the canvas Extend two I/O buses before and after the ROM modules by using “add wire” button (You will see thicker wires)IM Design VI Add bus taps by using “Add Bus Tap” button.You can change the direction of by selecting the orientation in the options window.IM Design VII Connect the taps to module pins by wireIM Design VIII Click on “Add Net Name”Then type the net name in the options window.Now you will see the name appear after the cursor.  Click on the wire you want to name.IM Design IX Name all the nets Double click on a ROM module, the property window will pop up. Change the INIT value and make it visible.IM Design X Click OK. You will see the initial value appears. Change the initial values for other ROM modules and save the diagram.IM Design XI Create a symbol for the instruction memory block.Instruction Decoder Design Create a new source, select VHDL moduleID Design II In the next window, you can type in your input/output signals for the instruction decoder, or you can skip it.ID Design III Next you’ll see a VHDL template which does nothing.ID Design IV Define the input and output signals of your instruction decoderDon’t copy this, YMMV!ID Design V Define the behavior the instruction decoder using process clause in VHDLID Design VI  Save and select the VHDL file Under the Design Utilities category in Process View, double click on Create Schematic Symbol Now the instruction decoder has been created and can be referenced in other designs Demo of the addition operation Show the simulation results for each of the 8