Lab 4 TutorialDesign of A Mini Load/Store Machine1.0 Introduction2.0 System Specification3.0 Design of System Architecture4.0 Design of the Instruction Memory4.1 Instruction Memory Initialization5.0 Design of the datapath component6.0 Design of the register file component7.0 Design of the instruction decoder8.0 Additional TipsUniversity of California San DiegoLab 4 TutorialDesign of A Mini Load/Store MachineCSE 140L, Fall 05Instructor: C.K. ChengComputer Science and EngineeringUniversity of California San DiegoNovember 25, 2005Ver Date By Description1 Nov. 25, 2005 Haikun Zhu, Rui Shi1.1 Nov. 27, 2005 Haikun Zhu Proofread1.2 Nov. 28, 2005 Haikun Zhu Corrected VHDL syntax error in Fig. 12. Thanks to Brian.1.3 Nov. 28, 2005 Haikun Zhu Modified Fig. 3; added missing control signal from the instruction decoder to the datapath.2CSE 140L FA05 - Lab 4 TutorialUniversity of California San Diego1.0 IntroductionThis tutorial tries to cover all the essential skills one will need to accomplish lab 4.2.0 System SpecificationPlease refer to the webpage of lab 4 assignment (http://www.cse.ucsd.edu/classes/fa05/cse140L/Lab4/lab4.htm) forthe system specification.3.0 Design of System ArchitectureWe start the design by working out the system architecture and interface signals between each components. Accord-ing to the specification, our mini computer system consists of the following five components:Program Counter The program counter is the address pointer for fetching the instructions in the instructionmemory.Instruction MemoryThe instruction memory can hold up to 16 instructions, each of which is 7-bit wide.Instruction DecoderThe instruction decoder is the control center of the whole system. It specifies whicharithmetic operation the datapath is going to execute, and takes care of the scheduling ofregisters.Datapath The datapath is a pure combinational module which performs the useful computing.Registers The registers, along with the instruction memory, provide operands for and receive theresults from the datapath.Since the capacity of the instruction memory is 16, we need a 4-bit address addr[3:0] from the program counter tohave complete access to the memory. Each instruction from the memory is dissembled into two parts: the higher 3bits instr[6:4] are sent to the instruction decoder to decide the operation of the next cycle. The lower four bitsinstr[3:0], which are the data portion of the instruction, are sent to the datapath for processing or stored in the regis-ters. The datapath can also receive a 4-bit operand from the register files; and the results, including a 4-bit numberand two flags (overflow and comparison) are stored back into the registers. The control signals emanating from theinstruction decoder are yet to be decided after the datapath and register files are fully studied.From the instruction set we find there are 4 arithmetic operations: ADD, SHIFT, Mask and COMP. Each of theformer three produces a 4-bit number. During each cycle, we need to make a decision that which of the three 4-bitnumbers is going to be stored back into the register files. Therefore, we will need a 2-bit control signal from theinstruction decoder to do this task. We then make a list of the sources and destinations of the four arithmetic opera-tions as shown in Table 1.Based on the above analysis we can design the structure of the datapath component as shown in Fig. 1.Table 1. Sources and destinations of the four arithmetic operationsoperation source destinationADD R1, R2 R3, overflow flagCOMP R1, R2 comparison flagSHIFT R1, instr[3:2] R3Mask R1, R2 R3CSE 140L FA05 - Lab 4 Tutorial3University of California San DiegoFIGURE 1. Structure of the datapath component.Next we make an analysis of the register usage according to the instruction set to see how the register file componentshould be designed. The source and destination of each register are listed in Table 2. Another important aspect aboutthe registers is that, each register should be enabled if and only if it is needed during the next clock cycle. Therefore,we will need five enable signals for all of the registers, and the enabled signals should be supplied by the instructiondecoder. The structure of the register file component is then shown in Fig. 2.FIGURE 2. Structure of the register file component.Table 2. Register usage table.register name source destinationR1 memory or datapath datapathR2 memory datapathR3 datapath nowhereoverflow flag register datapath nowherecompare flag register datapath nowhere4-bitShifter4-bitAdder4-bitMasker4-bitComparatorR1[3:0]R2[3:0]dpath_out[3:0](to R3[3:0])instr[3:2]sel[1:0]overflowcomparison(from instructionDecoder)R2 R1R3MUXdp ath_source [3:0]mem_source[3:0]R1_selR2[3:0]R1 [3:0]R3[3:0]OVL_in Comp_inComp_outOVL_outR2_enR1_enR3_enOVL_encom p_ en(from theinstruction decoder)4CSE 140L FA05 - Lab 4 TutorialUniversity of California San DiegoNow let us put everything together. Fig. 3 shows the architecture of whole mini computer system.FIGURE 3. System architecture of the mini load/store machine4.0 Design of the Instruction MemoryIn order to simplify the implementation, we use the ROM16x1 (Read-Only Memory) module from the Xilinx Libraryto realize the instruction memory. A ROM16x1 module has a 4-bit address, meaning that the depth of the storage is16, and the output is a single bit signal. We need seven ROM16x1 instances to implement the 16x7 instruction mem-ory. Given an address A3A2A1A0, the outputs of the seven ROM16x1 instances constitute an instruction. We use busto represent the address and instruction signals.FIGURE 4. ROM16x1 module from the xilinx library.There are two ways to create a bus in Xilinx. Suppose we already created an empty schematic called instr_mem.Before you place anything on the canvas, click menu Tools->Create I/O markers. You will be prompted to type in theinput/output signals, as shown in Fig. 5. However, the approach only works if the schematic is empty. Suppose wehave placed 7 ROM16x1 instances on the schematic, and want to add new buses addr[3:0] and instr[6:0]. Whatshould we do? Now here comes the trick. First draw a wire ( ) on the schematic, attach an I/O marker ( ) to it.Double click on the I/O marker to open the property window, in the name attribute row, type in addr[3:0]. You willsee the bus I/O marker and the wire become thicker since it’s now a bus signal. This method is shown in Fig. 6.ProgramCounterInstructionMemoryInstructionDecoderDa ta p