Lecture 6CSE 140LInstructor: C.K. Cheng11/02/2005Agendaz Summary of Lab1z Common issuesz Wisely use lab resourcesz Hints for Lab2z Lab3: Finite State Machinez Lab assignmentz Pattern Recognizerz Design flowz Tutorial on a simple designCommon issues for Lab1z Schematic entryz Wires cannot be connected into the input portz Wires cannot be connected out from the output port z Test benchz Generate Expected Simulation Resultsz Simulation waveforms in ModelSimz Please show the full name of signalsz Correct the errorsz Please mark the time delay using “insert cursor”z Keep consistency of the schematic diagram, test bench and simulation waveformsCommon issues for Lab1z Worst case delayA0A1A2A3B0B1B2B3CiS0S1S2S3Co4-bit adderworst case delay: B0 to CoCommon issues for Lab1z Worst case delayz Find some input combinationz Only changing B0 at time t1z At time t2, Co changes only because B0’s toggling goes through the longest pathz T = t2 – t1 is the worst case delay z A = 1111, B = 0000 → 0001, Ci = 0⇒ Co = 0 → 1Common issues for Lab1tA0A1A2A3B0B1B2B3CiCot1 t2Lab resourcesz Online lecture notes, tutorial, Q&Az Lab hoursz WebboardHints for Lab2z Design FlowSchematic entryBehavior simulationImplement designPost place&routesimulation•Design the circuit-- Combinational Logic-- Flip-Flops in Xilinx•Verify the function-- Setup clock Information in test bench•Timing analysis•Worst case analysisHints for Lab2z Use the given Flip-Flops and gatesz Three different Flip-Flops will be used:FDCE, FTCE, FDPEz In the post place & route simulation, the Flip-Flops will not function during the first 100ns of simulation time z The Flip-Flops in a Xilinx chip are held in reset/preset for the first 100ns. z Complete all tasks in the assignmentLab3 Assignmentz Design a pattern recognizerz Finite state machinez Mealy machine: produces an output for each transitionz Moore machine: produces an output for each statez Assignment different encodings for the statesz Comparison on # states, # FFs, # logic blocks,# lines in VHDL codesPattern RecognizerWhen x(t-2, t-1, t) = "011" or "011", z = 1;Otherwise z = 0; 001011XZ111011100110111tXZ01234567891011121314000001000110010Pattern RecognizerWhen x(t-2, t-1, t) = "011" or "011", z = 1;Otherwise z = 0; 001011XZ111011100110111tXZ01234567891011121314000001000110010Design Flowz Input state diagramz Layout of the designz Verify the functionState DiagramStateCADXilinx ISEFloorplannerModelSimTutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 101110101XZ0tXZ0123456789100S0: input pattern ‘0’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 101110101XZ01tXZ01234567891000S1: input pattern ‘1’StatesS0: input pattern ‘0’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 101011tXZ012345678910000S2: input pattern ‘11’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 1010110tXZ0123456789100001S3: input pattern ‘110’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 10101101tXZ01234567891000011S4: input pattern ‘101’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 101011010tXZ012345678910000110S5: input pattern ‘10’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 1010110100tXZ0123456789100001110S0: input pattern ‘0’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’S5: input pattern ‘10’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 10101101001tXZ01234567891000011000S1: input pattern ‘1’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’S5: input pattern ‘10’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 101011010010tXZ012345678910000110000S5: input pattern ‘10’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’S5: input pattern ‘10’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 1010110100101tXZ0123456789100001100001S4: input pattern ‘101’110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’S5: input pattern ‘10’Tutorial on a simple designz The pattern recognizer for tutorialz Recognize 110 and 10101101001010tXZ01234567891000011000010110101XZStatesS0: input pattern ‘0’S1: input pattern ‘1’S2: input pattern ‘11’S3: input pattern ‘110’S4: input pattern ‘101’S5: input pattern ‘10’S5: input pattern ‘10’State Diagram IS00Z=0S211Z=0S510Z=0S11Z=0S3110Z=1S4101Z=1010101011010Moore MachineRESETState Diagram IIS00S211S510S11S3110S4101010101011010Mealy MachineRESETState Diagram IIS00S211S510S11S3110S41010/01/00/01/00/11/00/01/01/00/01/10/0Mealy MachineRESETState Diagram IIS00S211S510S11S41010/01/00/01/00/11/01/00/01/10/0Mealy MachineRESETState Diagram IIS00S211S510S11S41010/01/00/01/00/11/01/00/01/10/0Mealy MachineRESETState Diagram IIS00S211S510S110/01/01/00/11/00/01/10/0Mealy MachineRESETState Diagram IIS00S211S510S110/01/01/00/11/00/01/10/0Mealy MachineRESETState Diagram IIS00S211S310S110/01/01/00/11/00/01/10/0Mealy MachineRESETStates EncodingS00S211S310S110/01/01/00/11/00/01/10/0RESET00011011Code211100100Code1S3S2S1S0Manual State Assignmentz Modify the VHDL program with state assignments.The VHDL codes look like the following:ARCHITECTURE BEHAVIOR OF MEALY ISTYPE type_sreg IS (s0,s1,s2,s3);attribute enum_encoding : string;attribute enum_encoding of type_sreg : type is "00 01 10 11";SIGNAL sreg, next_sreg : type_sreg;BEGIN ...Tutorial Designz Input Mealy/Moor state diagram in StateCADz Generate VHDL codesz Implement VHDL in Xilinxz Synthesisz Mappingz Place and