CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab CPU designTajana Simunic Rosing1Source: Vahid, Katz, CullerIntroduction• Programmable (general-purpose) processor– Mass-produced, then programmed to implement different processing tasksWellknown common programmable processors: PentiumSparcPowerPC•Well-known common programmable processors: Pentium, Sparc, PowerPC• Lesser-known but still common: ARM, MIPS, 8051, PIC– Low-cost embedded processors found in cell phones, blinking shoes, etc. – Instructive to design a very simple programmable processor• Real processors can be much more complexe2310Instruction2x40c0 c1 c2xt1xt0 xt2x(t) x(t-1) x(t-2)memoryPC IR0Data memory Dn-bit2x1Seatbelt warninglight single-purposeprocessorreg++∗∗∗ControllerRegister fileRFALUControl unitDatapath23-tap FIR filtersingle-purpose processorGeneral-purpose processorControl unitDatapathBasic Architecture• Processing generally consists of:–Loading some datag– Transforming that data– Storing that dataBasicdatapathUsef l circ it in aData memory D•Basic datapath: Useful circuit in a programmable processor– Can read/write data memory, where main sin-bit2x1data exists– Has register file to hold data locally–Has ALU to transform local datasiRegister file RFALUALUDatapath3Basic Datapath Operationspp• Load operation: Load data from data memory to RF• ALU operation: Transforms data by passing one or two RF register values through ALU performing operation (ADD SUB AND OR etc ) and writing back into RFALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF.• Store operation: Stores RF register value back into data memory• Each operation can be done in one clock cycleData memory DnbitData memory DnbitData memory DnbitRegister file RFn-bit2x1Register file RFn-bit2x1Register file RFn-bit2x1agALURegister file RFALUgALU4Load operationALU operation Store operationBasic Datapath Operationspp• Which are valid single-cycle operations for given datapath?– Move D[1] to RF[1] (i.e., RF[1] = D[1])StRF[1] t D[9] d t RF[2] t D[10]–Store RF[1] to D[9] and store RF[2] to D[10]– Add D[0] plus D[1], store result in D[9]aData memory DData memory D Data memory DRegister file RFn-bit2x1Register file RFn-bit2x1Register file RFn-bit2x1ALUALU ALULoad operationALU operation Store operation5pppBasic Architecture – Control Unit• D[9] = D[0] + D[1] – requires a sequence of four datapath operations:Data memory DInstruction memoryI0: RF[0]=D[0]1 RF[1] D[1]0: RF[0] = D[0]1: RF[1] = D[1]2: RF[2] = RF[0] + RF[1]3: D[9] = RF[2] •Each operation is aninstructionData memory Dn-bit1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Each operation is an instruction– Sequence of instructions – program– Store program in Instruction memory– Control unit reads each instruction and executes it on thedatapathRegister file RFnbit2x1PC IRexecutes it on the datapath• PC: Program counter – address of current instruction• IR: Instruction register – current instruction signals to control the datapathALUControllerDatapathControl unit6Basic Architecture – Control Unit• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.DecodeDetermine the operation and operands of the instruction–Decode –Determine the operation and operands of the instruction– Execute – Carry out the instruction's operation using the datapathInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]Instruction memoryIPCIR1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Data memory DD[0]: 99Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]RF[0]=D[0]0−>1ControllerPCIRRF[0]=D[0]PCIR1n-bit2x1PCIR3: D[9]=RF[2]RF[0]=D[0]1R[0]: ??Æ 99"load"Control unitController(a)FetchControl unitControllerRegister file RFALUController7Fetch(b)DecodeDatapathControl unit(c)ExecuteBasic Architecture – Control Unit• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.DecodeDetermine the operation and operands of the instruction–Decode –Determine the operation and operands of the instruction– Execute – Carry out the instruction's operation using the datapathInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]Instruction memoryIPCIR1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Data memory DD[1]: 102Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]RF[1]=D[1}1−>2ControllerPCIRRF[1]=D[1]PCIR2n-bit2x1PCIR3: D[9]=RF[2]RF[1]=D[1]2R[1]: ??Æ 102"load"Control unitController(a)FetchControl unitControllerRegister file RFALUController8Fetch(b)DecodeDatapathControl unit(c)ExecuteBasic Architecture – Control Unit• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.DecodeDetermine the operation and operands of the instruction–Decode –Determine the operation and operands of the instruction– Execute – Carry out the instruction's operation using the datapathInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]Instruction memoryIPCIR1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Data memory DInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]RF[2]=RF[0]+RF[1]2−>3ControllerPCIRRF[2]=RF[0]+RF[1]PCIR3n-bit2x1PCIR3: D[9]=RF[2]RF[2]=RF[0]+RF[1]3R[2]: ??Æ 201"ALU (add)"Control unitController(a)FetchControl unitControllerRegister file RFALUController991022019Fetch(b)DecodeDatapathControl unit(c)ExecuteBasic Architecture – Control Unit• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.DecodeDetermine the operation and operands of the instruction–Decode –Determine the operation and operands of the instruction– Execute – Carry out the instruction's operation using the datapathInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]Instruction memoryIPCIR1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Instruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]Data memory DInstruction memoryI0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]D[9]=?? Æ 201D[9]=RF[2]3−>4ControllerPCIRD[9]=RF[2]PCIR4n-bit2x1PCIR3: D[9]=RF[2]D[9]=RF[2]4R[2]: 201"store"Control