CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Flip FlopsTajana Simunic Rosing1Source: Vahid, KatzTiming: DefinitionsgTTT su 18T h 05D T su 1.8ns T h 0.5ns T w 331.8ns 0.5 ns T w 33Clk Q 3.3 ns T pd36T pd3.6 ns 1.1 ns3.3 ns dataDQ DQ• Cascaded FFs: 3.6 ns 1.1 ns 1.1 ns clock–Tpd> Th– Tperiod > Tpd + Tsu2Clock skewD-FF original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1CLK0INDQ DQCLK1100CLK1 is a delayedversion of CLK0InQ0Q1CLK0CLK1• Cascaded FFs: 3– Tpd > Tskew + Th– Tperiod + Tskew > Tpd + TsuMetastabilityyclkDaiDset up t imeviolationaiQviolationmetastablesynchronizer• Violating setup/hold time can lead to a metastable state– Metastable state: Any flip-flop state other than a stable 1 or 0Elll hbd’khihmetastablestate•Eventually settles to one or other, but we don’t know which– Fix: for internal circuits make sure to observe setup time; not possible for external inputs (e.g. button press)• Partial solutiona4– Insert synchronizer flip-flop for asynchronous input• flip-flop w very small setup/hold time, but doesn’t completely prevent metastabilityMetastabilityyveryProbability of flip-flop being metastable is…ailowverylowverylowincrediblylowsynchronizers• One flip-flop doesn’t completely solve problempppyp– Add more synchronizer flip-flops to decrease the probability of metastability–Can’tsolvecompletely–just decrease the likelihood of failure5Can t solve completely just decrease the likelihood of failureMetastability and asynchronous inputsyy p• Clocked synchronous circuits–inputs, state, and outputs sampled or changed in relation to a clock– e.g., edge-triggered FFs•Asynchronous circuitsAsynchronous circuits– inputs, state, and outputs sampled or changed independently of acommon reference signal (glitches/hazards a major concern)eg RSlatch–e.g., R-S latch• Asynchronous inputs to synchronous circuits– inputs can change at any time, will not meet setup/hold times– dangerous, synchronous inputs are greatly preferred– cannot be avoided (e.g., reset signal, memory wait, user input)6Synchronization failurelogic 1ylogic 0logic 1logic 0small, but non-zero probability that the FF output will get stuck in an in-between stateoscilloscope traces demonstratingsynchronizer failure and eventualdecay to steady stateyy• Occurs when FF input changes close to clock edge–the FF may enter a metastable state –neither a logic 0 nor 1 –7yg– it may stay in this state an indefinite amount of time– this is not likely in practice but has some probabilityDealing with synchronization failuregy• Reduce the probability of failure:– (1) slow down the system clock (2) use fastest possible logic technology in the synchronizer(3) cascade two synchronizers DDQQasynchronousinputsynchronizedinputClksynchronous systemClk•(1) slow down the system clock: this gives the synchronizer more time to decay into a () y g y ysteady state; synchronizer failure becomes a big problem for very high speed systems• (2) use fastest possible logic technology in the synchronizerthis makes for a very sharp"peak"upon which to balance8this makes for a very sharp peak upon which to balance• (3) cascade two synchronizers this effectively synchronizes twice (both would have to fail)Handling asynchronous inputsClocked Synchronous SystemSynchronizergy pD QQ0ClockAsync InputSystemD QQ0ClockAsync InputD QD QClockCl kQ1D QClockCl kQ1ClockClockIn is asynchronous and fans out to D0 and D1one FF catches theInQ09one FF catches the signal, one does notinconsistent state may be reached!Q1CLKGlitchingg• Glitch: Temporary values on outputs that appear soon after input changes, before stable new output values• Designer must determine whether glitching outputs may pose a problempose a problem– If so, may consider adding flip-flops to outputs• Delays output by one clock cycle, but may be OK10CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Counters and FSMsTajana Simunic Rosing11Source: Vahid, KatzMobius Counter in VeriloggDQDQDQDQOUT1 OUT2 OUT3 OUT4DQDQDQDQINCLKinitialbeginA = 1’b0;B=1’b0;B = 1 b0;C = 1’b0;D = 1’b0;endalways @(posedge clk)beginA <= ~D;B <= A;C<=B;12C <= B;D <= C;endLight Game FSMg•Tug of War gameTug of War game– 7 LEDs, 2 push buttons (L, R)RESETLED(3)LED(2)LED(1)LED(0)LED(6)LED(5)LED(4)RRRRR()()()()()()()LLLLL13Light Game FSM Verilogggmodule Light_Game (LEDS, LPB, RPB, CLK, RESET);input LPB ;input RPB ;combinational logicinput RPB ;input CLK ;input RESET;output [6:0] LEDS ;wire L, R;assign L = ~left && LPB;assign R = ~right && RPB;assign LEDS = position;greg [6:0] position;reg left;reg right;assign LEDS = position;sequential logicreg right;always @(posedge CLK)begin left <= LPB;ihright <= RPB;if (RESET) position <= 7'b0001000;else if ((position == 7'b0000001) || (position == 7'b1000000)) ;else if (L) position <= position << 1;else if (R) position <= position >> 1;14else if (R) position <= position >> 1; endendmoduleFinite string pattern recognizer• Output a 1 when …010… appears in a bit string, and stop when …100 appearsstop when …100 appearsS0[0]10resetS4[0]S1[0]1010...1...01011...01S2[0]10S5[0]00...10111...010 ...1000 or 1S3[1]00S6[0]15Finite string pattern recognizer in Veriloggp g g• Verilog description including state assignmentmodule string (clk, X, rst, Q0, Q1, Q2, Z);input clk, X, rst;always @(posedge clk) beginif (rst) state = S0;output Q0, Q1, Q2, Z;parameter S0 = [0,0,0]; //reset stateparameter S1 = [0,0,1]; //strings ending in ...0parameter S2 = [0,1,0]; //strings ending in ...01elsecase (state)S0: if (X) state = S4 else state = S1;S1: if (X) state = S2 else state = S1;S2: if (X) state = S4 else state = S3;parameter S3 = [0,1,1]; //strings ending in ...010parameter S4 = [1,0,0]; //strings ending in ...1parameter S5 = [1,0,1]; //strings ending in ...10parameter S6 = [1,1,0]; //strings ending in ...100S3: if (X) state = S2 else state = S6;S4: if (X) state = S4 else state = S5;S5: if (X) state = S2 else state = S6;S6: state = S6;default: beginreg state[0:2];assign Q0 = state[0];assign Q1 = state[1];assign Q2 = state[2];de au t: beg$display (“invalid state reached”);state = 3’bxxx;endendcaseend16assign Q2 = state[2];assign Z = (state == S3);endendmoduleController Design3.4g• Five step controller design process17Laser Timer3.3•