CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Timing, Mux, Demux, AddersTajana Simunic Rosing1Outline• Non-ideal gate behavior (3.5)– Rise/fall time– Delay– Pulse width• Pass gates (Appendix B)g(pp )• Muxes & Demuxes (chap 4.2 pp. 171-183)• Adders (chap 5.6)2Charge/discharge in CMOSgg• Calculate on resistance•Calculate capacitance of the gates circuit is drivingCalculate capacitance of the gates circuit is driving• Get RC delay & use it as an estimate of circuit delay–Vout= Vdd( 1- e-t/RpC)3Source: Prof. Subhashish MitraTime behavior of combinational networks• Waveforms–visualization of values carried on signal wires over timeg– useful in explaining sequences of events (changes in value)• Simulation tools are used to create these waveforms–input to the simulator includes gates and their connectionsinput to the simulator includes gates and their connections– input stimulus, that is, input signal waveforms• Some terms–gate delay—time for change at input to cause change at output–gate delay —time for change at input to cause change at output• min delay – typical/nominal delay – max delay• careful designers design for the worst case–rise time — time for output to transition from low to high voltagepgg– fall time — time for output to transition from high to low voltage– pulse width — time that an output stays high or stays low between changesNon-Ideal Gate Behavior – DelayaFaFaFaTime• Real gates don’t respond immediately to input changes– Rise/fall timeDelay5–Delay– Pulse widthWaveform view of logic functionsg• Just a sideways truth table–but note how edges don’t line up exactlytimegpy– it takes time for a gate to switch its output!time6change in Y takes time to "propagate" through gatesMomentary changes in outputsyg p• Can be useful — pulse shaping circuits•Can be a problem—incorrect circuit operationFABCDCan be a problem incorrect circuit operation (glitches/hazards)• Example: pulse shaping circuitF–A’ • A = 0– delays matterFi l 0D remains high for7F is not always 0pulse 3 gate-delays wideD remains high forthree gate delays afterA changes from low to highOscillatory behavior+y• Another pulse shaping circuitopen switchresistorABCinitiallyclose switchswitchDinitially undefinedopen switchCSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems Muxes and demuxesTajana Simunic Rosing9Pass transistor – Mux building block• Connects X & Y when A=1, else X & Y disconnected– A_b = not(A)10Fig source: Prof. Subhashish MitraMultiplexor (Mux)p()• Mux routes one of its N data inputs to its one output, based on binary value of select inputsyp• 4 input mux Æ needs 2 select inputs to indicate which input to route through• 8 input mux Æ 3 select inputs • N inputs Æ log2(N) selects11Mux Internal Design2×1i02×1i02×1i0AYAAi1i0s01di1i0s00di1i0s0dABYYABAB2x1 mux• Selects input to connect to Y– selA == 1: connects A to Y–selB == 1: connects B to Y12Fig source: Prof. Subhashish MitraMultiplexers/selectorsp• 2:1 mux: Z = A'I0+ AI1•4:1 mux:Z=A'B'I0+A'BI1+AB'I2+ ABI34:1 mux:Z ABI0+ ABI1+ AB I2+ ABI3• 8:1 mux: Z = A'B'C'I0+ A'B'CI1+ A'BC'I2+ A'BCI3+AB'C'I4+ AB'CI5+ ABC'I6+ ABCI72 -1I0I1k=0n• In general:Z = Σ (mkIk)I1I2I3I4I58:1muxZI00– in minterm shorthand form for a 2n:1 MuxI5I6I7ABCI0I1I2I34:1muxZI0I12:1muxZ13A B CA BAN-bit Mux Examplep• Four possible display itemsTt(T)A illl (A) I t t (I)–Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide– Choose which to display using two inputs x and y–Use 8-bit 4x1 mux14Use 8bit 4x1 muxMultiplexers as general-purpose logicpgpp g•A 2n-1:1 multiplexer can implement any function of n variables– with n-1 variables used as control inputs and– the data inputs tied to the last variable or its complement• Example: F(A,B,C) = m0 + m2 + m6 + m715Demultiplexers/decodersp• Decoders/demultiplexers: general concept–single data input, n control inputs, 2noutputsgp, p,p– control inputs (called “selects” (S)) represent binary index of output to which the input is connected–data input usually called“enable”(G)1:2 Decoder:O0 = G • S’O1 = G•S3:8 Decoder:data input usually called enable (G)O1 = G •S 2:4 Decoder: O0 = G•S1’•S0’3:8 Decoder: O0 = G • S2’ • S1’ • S0’O1 = G • S2’ • S1’ • S0O2 = G • S2’ • S1 • S0’O3 = G•S2’•S1•S0O0 = G •S1 •S0O1 = G • S1’ • S0O2 = G • S1 • S0’O3 = G • S1 • S0O3 = G •S2 •S1 •S0O4 = G • S2 • S1’ • S0’O5 = G • S2 • S1’ • S0O6 = G • S2 • S1 • S0’O7 = G•S2•S1•S016O7 = G •S2 •S1 •S0Gate level implementation of demultiplexerspp• 1:2 decoders• 2:4 decoders17Demultiplexers as general-purpose logic (cont’d)• F1 = A'BC'D + A'B'CD + ABCD• F2 = ABC'D' + ABC• F3 = (A' + B' + C' + D')0 A'B'C'D'1 A'B'C'D2A'B'CD'3A'B'CD4A'BC'D'5A'BC'D6A'BCD'7A'BCD7A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11AB'CD4:16DECEnable11ABCD12 ABC'D'13 ABC'D14 ABCD'15ABCD18ABCDMux and demux combination• Uses in multi-point connectionsB0 B1A0 A1multiple input sourcesMUXABSa SbMUXABSummultiple output destinationsSsDEMUX19S0 S1Mux example: Logical function unitpg• Multi-purpose function block–3 control inputs to specify operation to perform on operandsppyp p p– 2 data inputs for operands– 1 output of the same bit-width as operandsC0 C1 C2 Function Comments0001always 100001always 1001A + B logical OR0 1 0 (A • B)' logical NAND0 1 1 A xor B logical xor12348:1 MUXF1 0 0 A xnor B logical xnor1 0 1 A • B logical AND1 1 0 (A + B)' logical NOR1110always 04567S2 S1 S0201110always 0C2C0 C1CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems Arithmetic circuitsTajana Simunic Rosing21Example: 4-bit binary adderpy• Inputs: A, B, Carry-in•Outputs: Sum Carry-outAAAAACinCoutOutputs: Sum, CarryoutABCoutSAAAAABBBBBSSSSSCinCouta3FAb3 a2b2cibaFAcibaa1b1FAcibaa0 b0 ciFAcibaco scos3 s2 s1co s co ss0co s(a)22Ripple-carry adder critical delay pathABCinCout@0@0@N@1@N+14 stageadderA00S0 @2ppyypABCout@0@0@@1@N+2B0A1B1C1 @2S1 @3C2 @4latearrivingsignaltwo gate delaysto compute CoutB1A2B2C2 @4S2 @5C3 @6B2A3B3C3 @6S3 @7Cout @8S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 ValidCout @823T0 T2 T4 T6