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UCSD CSE 140L - Altera Quartus II Tutorial

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Altera Quartus II TutorialCSE140L – WI06TA: Jianhua LiuCSE Dept. UCSDAltera Quartus IIz The Quartus II development software provides a complete design environmentfor FPGA designs. z Design entry using schematics, block diagrams, VHDL, and Verilog HDL . z Design analysis and synthesis, fitting, assembling, timing analysis, simulation.Altera Quartus IIDesign flow• Design entry• Analysis andsynthesis• Fitting• Assembling• Timing analysis• SimulationQuartus II• HDL editor• Block diagram,schematic editor• Compiler tool• Compilation report• Timing closure floorplan• Simulator tool• Waveform editorTutorial Outlinez Open Quartus II and pick a device.z Build a full adder. (Block/Schematic)z Add componentsz Add portsz Add connections (single wire connection)z Build a 4-bit adder.z Create a block for full adderz Use conduit and port mappingTutorial Outlinez Compile the 4-bit adder.z Open compiler toolz Read compilation reportz Open timing closure floorplanz Simulate the 4-bit adder.z Open simulator toolz Edit simulation waveformz Observe simulation resultsz Schematic for 16-bit Multiplexerz Use connections by nameStart Quartus IIz Open Quartus II, click on the icon Work spaceProject NavigatorMessage windowCreate a new projectz Menu Æ File Æ New Project WizardBuild a full adderz Menu Æ File Æ Newz Create a Block Diagram/Schematic Filez Menu Æ File Æ Save As: fadder.bdfLibraryNew BlockSingle WireBusConduitBuild a full adderz Click on libraryz Find xor under primitives Æ logicBuild a full adderz Place two xor, two and2 and one or2.Build a full adderz Find input and output under primitives Æ pin, and place three input and two outputz Double click on each pin, to change pin name.Build a full adderz Connect them by single wirez Save the fileQuestionsBuild a 4-bit adderz Menu Æ File Æ Newz Create a Block Diagram/Schematic Filez Menu Æ File Æ Save As: adder4.bdfz Click on new block , and draw a block.z Double click on the block name, change it to fadderBuild a 4-bit adderz Right click on the block, and select Block Properties in the pop-up menu. z In the tag I/Os, add the following ports:Build a 4-bit adderz Click on OK to dismiss the properties window.z Right click on the block, and select AutoFit in the pop-up menu.z Select the block, make four copies by copy/paste.z Add 3 inputs and 2 outputs.Build a 4-bit adderz Use conduit tool to connect each fadder to inputs and outputs. Conduit can stop at any point on a block border.Build a 4-bit adderz The primary input Cin is automatically connected to the Cin port of inst by the same same. z Right click on the conduit, select properties, the connection can be found in the tab Signals.Build a 4-bit adderz For A[3..0], B[3..0] and S[3..0], port mapping should be manually defined. Edit the signals property for A[3..0] like this:Build a 4-bit adderz After port mapping for A[3..0], B[3..0] and S[3..0], you will see this:Build a 4-bit adderz Place single wires for carry signals.Build a 4-bit adderz Double click on a port mapper , and define port mapping in the tab Mappings. For example, map Coutto signal C1.Build a 4-bit adderz Here’s the final diagram.QuestionsCompile the designz Menu Æ Tools Æ Compiler Toolz Click on Start. The design will be compiled automatically.Compile the designz Click on Report button after compilation.Compile the designz Worst delay can be found in Timing Analyzer reportCompile the designz Select the worst delay, right click on it, and select locate in the pop-up menu Æ Locate in Timing Closure Floorplan. You can see the design implementation in the FPGA device.Simulate the designz Menu Æ Tools Æ Simulator Toolz Type adder4 for Simulation inputSimulate the designz Click on Open button , and save the file as adder4.vwfSignals WaveformsSimulate the designz Double click on signals area, and click the button Node Finderz List all the pins and select the primary inputs and outputs, then click OK.Simulate the designz To change the value of each input, right click on the input and select value in the pop-up menu.Simulate the designz Set value to each inputs and save the file.Simulate the designz Go back to the simulator tool, and click on the button Start . adder4.vwf will be updated after the simulation.Simulate the designz The correctness of the design is verified, and the worst delay can be identified.QuestionsSchematic for 16-bit Multiplexerz The schematic diagram of a 4-bit Multiplexer. Note that the wires connected by name.Schematic for 16-bit Multiplexerz To name a wire/bus, right click the wire/bus, select properties in the pop-up menu, and then fill in the name.Schematic for 16-bit Multiplexerz The schematic diagram of a 16-bit


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