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UCSD CSE 140L - Introduction

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CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab IntroductionTajana Simunic Rosing1Welcome to CSE 140L!• Course time: W 2-2:50pm, WLH 2205•Discussion session:F12-12:50pmCSE 3219•Discussion session: F 12-12:50pm, CSE 3219• Instructor: Tajana Simunic Rosing• Email: [email protected]; please put CSE140L in the subject line• Ph. 858 534-4868•Office Hours:Tu/Th1-2pmCSE 2118•Office Hours: Tu/Th1-2pm, CSE 2118• Instructor’s Assistant: Sheila Manalo – Email: [email protected]– Phone: (858) 534-8873 •TA: Ling Zhang•TA: Ling Zhang – Email: [email protected]– Office hours: M 2-3pm; W 10-11am in CSE 3219• TA: Chun Chen Liu–Email:chl084@ucsd edu–Email: [email protected]– Office hours: T 10am-12pm in CSE 3219• Class Website:– http://www.cse.ucsd.edu/classes/sp08/cse140L/•Grades:http://webct ucsd edu2Grades: http://webct.ucsd.eduCourse Descriptionp• Prerequisites:– CSE 20 or Math 15A, and CSE 30. – CSE 140 must be taken concurrently• Objective:–Introduce digital components and system design concepts throughIntroduce digital components and system design concepts through hands-on experience in a lab• Grading–Labs (4): 70%Labs (4): 70%• We have 15 Xilinx platforms with PCs – organize in teams of two• Schedule for lab access; need to schedule a demo to TA by lab due date• Go to Robin Knox [[email protected]] office in CSE 2248 to program your student ID for access to CSE 3219your student ID for access to CSE 3219– Monday-Thursday 10-12:30 and 2:00-4:00– Final exam: 30%–Regrade requests: turn in a written request at the end of the class 3gwhere your work is returnedTextbook and Recommended Readingsg• Required textbook:–Contemporary Logic Design byContemporary Logic Design by R. Katz & G. Borriello• Recommended textbook:– Digital Design by F. Vahid• Lecture slides are derived from the 4slides designed for both booksHardware we will use• Freely available in CSE 3219 lab:–XilinxVirtex-II Pro Development SystemXilinx Virtex-II Pro Development System (XUPV2P)http://www.xilinx.com/univ/xupv2p.htmlPC in the lab already have ISE tools installed–PC in the lab already have ISE tools installed. You can program boards in the lab only!– You can download on your own PC Webpackto implement and test your design beforeto implement and test your design before programming the boardwww.xilinx.com/ise/logic_design_prod/webpack.htm• Alternative: Altera Board you can buy in the bookstore for $1005Outline• Introduction to Xilinx board & tools• Transistors– How they work– How to build basic gates out of transistors–How to evaluate delayHow to evaluate delay• Pass gates• Muxes6Basic FPGA ArchitectureOverview• All Xilinx FPGAs contain the same basic resourcesresources– Slices grouped into configurable logic blocks - CLBs• Contain combinatorial logic and register resources– Input/Output Blocks - IOBs• Interface between the FPGA and the outside worldPblitt–Programmable interconnect– Other resources•ProcessorProcessor• Memory• MultipliersGlbl l kbff•Global clock buffers• Boundary scan logicVirtex-II ArchitectureI/O Blocks (IOBs)I/O Blocks (IOBs)Block SelectRAM™Block SelectRAM™resourceresourceProgrammableProgrammableCfi blCfi blDedicated multipliersDedicated multipliersProgrammable interconnectProgrammable interconnectConfigurableLogic Blocks (CLBs)ConfigurableLogic Blocks (CLBs)Clock Management (DCMs, BUFGMUXes)Clock Management (DCMs, BUFGMUXes)(DCMs, BUFGMUXes)(DCMs, BUFGMUXes)Slices and CLBs• Each Virtex™-II CLB if liCOUTCOUTcontains four slices– Local routing provides feedback between slicesBUFTBUF TCOUTCOUTSlice S3feedback between slices in the same CLB, and it provides routing to ihb i CLBSwitchMatrixSlice S2SHIFTneighboring CLBs– A switch matrix provides accessSlice S1access to general routing resourcesCINSlice S0Local RoutingCINSimplified Slice Structurep• Each slice has four Slice 0outputs– Two registered outputs, two non-registered outputsLUTLUT CarryCarryDQCEPRECLRgp– Two BUFTs associated with each CLB, accessible by all 16 CLB outputsLUTLUTCarryCarryDPREyp• Carry logic runs vertically, LUTLUTCarryCarryDQCECLRup only– Two independent carry chains per CLBBasic Architecture 11carry chains per CLBDetailed Slice Structure• The next few slides discuss the slicediscuss the slice features–LUTs– MUXF5, MUXF6, MUXF7, MUXF8 (only the F5 and F6 MUX are shown in this diagram)– Carry Logic– MULT_ANDs– Sequential ElementsBasic Architecture 12Look-Up Tablesp• Combinatorial logic is stored in Look-Up Tables (LUTs)ABCDZTables (LUTs) – Also called Function Generators (FGs)– Capacity is limited by the number of inputs, ABCDZ0000000010not by the complexity• Delay through the LUT is constant001000011101001Combinatorial LogicA0100101011...BCDZ110001101011100Basic Architecture 131110011111Connecting Look-Up TablesgpMUXF8 combines the twoF5F8CLBSlice S3MUXF8 combines the two MUXF7 outputs (from the CLB above or below)MUXF6 bi liF5F6Slice S2MUXF6 combines slices S2 and S3Slice S1F5F7MUXF7 combines the two MUXF6 outputsSlice S0F5F6MUXF6 combines slices S0 and S1MUXF5 combines LUTs in each sliceBasic Architecture 14Fast Carry Logicyg•Simple, fast, andCOUTCOUTSimple, fast, and complete arithmetic Logic–Dedicated XOR gate To S0 of the next CLBTo CIN of S2 of the next CLBFirst CarrySLICE S3gfor single-level sum completion– Uses dedicated tiFirst Carry ChainSLICE S2COUTCINrouting resources – All synthesis tools can infer carry logicSLICE S1Second S2COUTCINSLICE S0Carry ChainCOUTCINCINCLBBasic Architecture 15CINCINCLBFlexible Sequential ElementsFDRSE1q• Either flip-flops or latchesTi hli ihtiDCESRQFDRSE_•Two in each slice; eight in each CLB•Inputs come from LUTs orDCEPRE QFDCPEInputs come from LUTs or from an independent CLB inputSttdtCLRLDCPE•Separate set and reset controls–Can be synchronous or DCEPRECLRQGyasynchronous• All controls are shared within a slicea slice– Control signals can be inverted locally within a sliceMULT_AND Gate• Highly efficient multiply and add implementation–Earlier FPGA architectures require two LUTs per bit to perform the qppmultiplication and addition– The MULT_AND gate enables an area reduction by performing the LUTCY MUXAmultiply and the add in one LUT per bitCODI CISCY_MUXCY_XORMULT_ANDAAxBBA x BLUTLUTBLUTIOB Element• Input


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UCSD CSE 140L - Introduction

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