CS 140L Lecture 8 System DesignLab4. System DesignSlide 3Slide 4Overview of System DesignSlide 6Control SubsystemSlide 81CS 140L Lecture 8System DesignProfessor CK ChengCSE Dept.UC San Diego2Lab4. System DesignInst(Data)R1R2R3OutputData PathControl Subsystem3Three instruction bits and 4 data bits. I2I1I0D3D2D1D0id I2 I1 I0 Op0 0 0 0 Init1 0 0 1 Move 12 0 1 0 Move 23 0 1 1 Store4 1 0 0 Add5 1 0 1 Shift6 1 1 0 Comp7 1 1 1 MaskInstruction Set4•Init: R1 = R2 = R3 = (0,0,0,0) Initialize all three registers to 0•Mov1: R1 = (D3, D2, D1, D0)Move data D3-0 to R1•Mov2: R2 = (D3, D2, D1, D0)Move data D3-0 to R2•Store: R2 <= R3Store data into R2 from R3•Add: R3 <= R1 + R2, Overflow flagAdd R1 and R2 and store the sum in R3•Shift: R3 <= (R2 Shift left by (D3, D2) bits)Shift R2 by D3-2 bits and store the result in R3•Comp: flag(R1, R2) <= 1 iff R1>R2Compare R1 and R2 and set flag=1 if R1 is bigger•And: R3 <= (R1)&(R2)AND bitwise R1 and R2. Store the result in R3Instruction Set5Overview of System DesignD0D1D2D3I0I1I2Data InputD3-0Control InputI2-0, D3-2ControlSignalsConditionsData outputControl outputDataSubsystemControlSubsystem6R2D3-001S0En2 CLRR1CLR+<<Comp&01S5FlagS4S3En10123R3En3CLRDataS2S1clkoverflowclkData Path Subsystem7Control SubsystemControlSubsystemD2D3I0I1I2CLREn1En2En3S0S1S2S3S4S58Control SubsystemI2-0 Clr En1-3S2S1S0S5S4S3CLR 000 1 --- -- - - --Move1 001 0 100 -- - - --Move2 010 0 010 -- 0 - --Store 011 0 010 -- 1 - --+ 100 0 001 00 - 0 --<< 101 0 001 01 - - D3D2Comp 110 0 000 -- - 1 --& 111 0 001 11 - -
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