1CSE140 LInstructor: Thomas Y. P. LeeFebruary 8, 2006Agenda Asynchronous Counter Synchronous Counter Gray Counter Johnson Counter Pseudo Random Sequencer Binary Counter Converting Between FFs Minimum Clock Period Clock Skew2Issues  TA Office Hours and Lab Hours Why we want to build some digital circuits already exist in Altera Library? Lab3 – Vending Machine Lab4 – TA will have one to one meeting and oral presentation on lab reportCounter A Counter counts the number of clock cycles- Up/down counting3Asynchronous and Synchronous Counter Asynchronous counterNo universal global clock signalLess area−You have more flexibility in designing FSMsLess power−Eliminates simultaneous D flip-flop switching during clock transitionsHigh speed−In terms of throughputBut …hard to design and error prone−Complicate protocol for inter-module communication−TimingSynchronous counterAll flip-flops are governed by a universal global clock signalAsynchronous Counter0000100000101010010D0D1D2D3CLK010011001234567891011121314151611100001100101011101001110110111111100001This is the result that we would like to see:Up CounterDown Counterhttp://www.play-hookey.com/digital4Asynchronous Counter (Cont.)VerificationSynchronous CounterExample of Synchronous CounterGray CounterJohnson CounterBinary Counter (Up/Down)Serial enable logicLSBMSB5Synchronous Counter (cont.)LSBMSBParallel enable logicSynchronous Counter0000100000101010010D0D1D2D3CLK010011001234567891011121314151611100001100101011101001110110111111100001This is the result that we would like to see:6Synchronous Counter (Cont.)CLKDQCLKD0DQCLKD1• D0i= D0’i-1• D1i= D0i-1⋅D1’i-1+ D0’i-1⋅D1i-1 = D0i-1⊕D1i-1• D2i= ?• D3i= ?D1What is Gray Code? What is Gray Code?Gray code is a number representation, Invented by Emile Baudot (1845-1903) Grade Code Algorithm1. For G0, write one 0s followed by two 1’s, two 0’s, and so on2. For G1, wrie two 0s followed by alternating groups of four 1s and four 0s3. For Gn, start by writing 2n0s, then write alternating groups of 2n+11s and 0s1 0 0 01 1 1 1151 0 0 11 1 1 0141 0 1 11 1 0 1131 0 1 01 1 0 0121 1 1 01 0 1 1111 1 1 11 0 1 0101 1 0 11 0 0 191 1 0 01 0 0 080 1 0 00 1 1 1701 0 10 1 1 060 1 1 10 1 0 150 1 1 00 1 0 0 40 0 1 00 0 1 130 0 1 10 0 1 020 0 0 10 0 0 110 0 0 00 0 0 00G3 G2 G1 G0B3 B2 B1 B0Gray Code NumberBinary NumberDecimal Number7What is Gray Code? (Cont.)0 0 0 00 0 0 10 0 0 00 0 0 10 0 1 10 0 0 00 0 0 10 0 1 10 0 1 00 0 0 00 0 0 10 0 1 10 0 1 00 1 1 00 0 0 00 0 0 10 0 1 10 0 1 00 1 1 00 1 1 1a b c d eStart with 0, change the least significant bit that forms a new code wordGray CounterEvery two neighboring states differ in one bitMay reduce hazards in digital circuitThe following is the result that we would like to see:0000100001101110100D0D1D2D3CLK1100010012345678910111213141516001000111011111101110101110110010001000018Gray Counter (Cont.)State Transition Table from Gray Code Couning00000001000110011001110111010101010101110111111111111011101100110011001000101010101011101110011001100100010011001100100010000000Next State of D0, D1, D2, D3Present State of D0, D1,D2,D301111111010101111111101110110011100111011101010100011001000000011010111011100110001010100011001001001100011001001100100010000000Outputs (Next) of D3,D2,D1, D0Inputs (Present) of D3, D2, D1, D0Corresponding Truth Table of StatesGray Counter (Cont.)D3 D2XX111010X11101XX01X00000D1 D010110100(D3) next = D3.D1’ + D3.D0’ + D3’.D2.D0Implement with D Flip FlopsD3 D2XX101010X11110XX01X10000D1 D010110100(D2) next= D2’.D1 + D2.D0’ + D3.D2’.D09Gray Counter (Cont.)D3 D2XX001010X11110XX01X11000D1 D010110100Implement with D Flip Flops(D1) next= D2.D0’ + D3’.D2’.D0D3 D2XX011010X01110XX01X01100D1 D010110100(D0) next= D3’.D1’ + D1.D0’ + D3. D2’.D0’Gray Counter (Cont.)111011111101110010110100T0D0D1D2D3T0next=(D0⊕D1⊕D2⊕D3)’101110110010110100T2D0D1D2D3T2next=D0’⋅D1⋅(D2⊕D3)’T1=? T3=?Hint: What if we use T Flip-Flop10Johnson Counter• Johnson Counter - “Twisted ring” counter or Mobius Counter• Last output inverted and feed back to the first inputBinary Counterhttp://www.play-hookey.com/digital What is the worse case time delay of this counter?Assume J-K FF propagation delay = 8ns AND gate delay = 5 nsThink about Divide-by-3, Divide-by-5 Counter Design?11Pseudo Random Sequencer1111011110000100000D0D1D2D3CLK0011000112345678910111213141516100111000110101101011010110111101111011111412812493613105117151415A pseudo random sequencer generates a sequence of pseudo random bit patternNot completely random, it’s cyclic bit sequence with a large periodImplemented with Linear Feedback Shift Register (LFSR) or called LFSR Counter2n- 1 states before repeating, n is number of bitsThe length cycle depends on (1) Initial State (2) Feedback networkUsed in CRC check, VLSI built-in self testing, CPU clock measurement, high speed modems and network interface (100MPS Ethernet) to scramble/descramble the dataPseudo Random Sequencer (Cont.)See table for feedback eq of all nReference:John F. Wakerly: Digital Design Principles and Practices, section 8.5.812Pseudo Random Sequencer (Cont.)Converting Between FFsz Q+ means “the next value of Q.“Excitation” is the input that determines the next state.z “Characteristic equation” specifies the next state of a device as a function of its excitation.z S-R latch: Q+ = S + R´·Q13Timing Parameter – Minimum Clock PeriodWe must haveT > Tcq+T logic+ TsuTlogic: contamination or minimum delay through logic network T su: setup time of FF Thold: hold time of FFClock SkewHow to overcome Clock Skew? Tcq,cd+ T logic,cd> Thold+ δδ : The differences between arrival times of the clock at different devicesTcq, cd: contamination or minimum delay from Clock to q Tlogic,cd: contamination or minimum delay through logic network T su: setup time of FF Thold: hold time of