CSE140L: Components and Design Techniques for Digital Systems Lab Techniques for Digital Systems Lab Tajana Simunic Rosing1Source: Vahid, Katz, CullerUpdates & Outlinep• Grade distribution:–70% Labs• 35% Lab 4• 30% Lab 3•20% Lab 2%• 15% Lab 1– 30% Final exam•FinalexamFridayJune13that 3pm same location as•Final exam –Friday, June 13th, at 3pm, same location as the class– Everything covered in labs, lectures, book & handouts– Format: • Multiple choice and/or T/F questions on the assigned reading and labs• Problems to solve based on the lectures, labs and textbook4CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab SynthesisTajana Simunic Rosing5Source: Vahid, Katz, CullerLogic Synthesis • Verilog and VHDL started out as simulation languages, but soon programs were written to automatically convertVerilogcode into lowprograms were written to automatically convert Verilogcode into low-level circuit descriptions (netlists).SthiVerilogcircuitSynthesisToolVerilogHDLcircuitnetlist• Synthesis converts Verilog (or other HDL) descriptions to an implementation using technology-specific primitives:– For FPGAs: LUTs, flip-flops, and RAM blocks– For ASICs: standard cell gate and flip-flop libraries, and memory blocks6Why Perform Logic Synthesis?ygy1. Automatically manages many details of the design process:•Fewer bugsFewer bugs• Improves productivity2. Abstracts the design data (HDL description) from any particular implementation technologyimplementation technology• Designs can be re-synthesized targeting different chip technologies; E.g.: first implement in FPGA then later in ASIC3In some cases leads to a more optimal design than could be3.In some cases, leads to a more optimal design than could be achieved by manual means (e.g.: logic optimization)7How Does It Work?• Variety of general and ad-hoc (special case) methods:–Instantiation: maintains a library of primitive modules (AND, OR, etc.) and yp ()user defined modules– “Macro expansion”/substitution: a large set of language operators (+, -, Boolean operators, etc.) and constructs (if-else, case) expand into il i itspecial circuits– Inference: special patterns are detected in the language description and treated specially (e.g.,: inferring memory blocks from variable declaration and read/write statements FSM detection and generation from“always @and read/write statements, FSM detection and generation from always @ (posedge clk)” blocks)– Logic optimization: Boolean operations are grouped and optimized with logic minimization techniques– Structural reorganization: advanced techniques including sharing of operators, and retiming of circuits (moving FFs), and othersOperatorsp• Logical operators map into primitive logic gatesY = ~X << 2gates• Arithmetic operators map into adders, subtractors, …– Unsigned 2s complementX[3]Y[5]–Model carry: target is one-bit wider that source• Relational operators generate comparatorsX[0]X[1]X[2]Y[3]Y[4]• Shifts by constant amount are just wire connections– No logic involved•Variable shift amounts a whole differentY[1]Y[2]X[0]•Variable shift amounts a whole different story --- shifter• Conditional expression generates logic or MUXY[0]Synthesis vs. CompilationypLevels of Representation• Compiler – Recognizes all possible constructs in a formally defined61CHigh Level Language Program (e.g., C)Compilertemp = v[k];v[k] = v[k+1];v[k+1]=temp;constructs in a formally defined program language– Translates them to a machine language representation of Assembly Language Program (e.g.,MIPS)CompilerAssemblerv[k 1] temp;lw $to, 0($2)lw $t1, 4($2)sw$t1, 0($2)sw$t04($2)execution process• Synthesis– Recognizes a target dependent subset of a hardwareMachine Language Program (MIPS)Machine Interpretationsw$t0,4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111subset of a hardware description language– Maps to collection of concrete hardware resources15Control Signal SpecificationMachine Interpretation°°–Iterative tool in the design flow105Simple Exampleppmodule foo (a,b,s0,s1,f);input [3:0] a;input [3:0] b;input [3:0] b;input s0,s1;output [3:0] f;reg f;always @ (a or b or s0 or s1)if (!s0 && s1 || s0) f=a; else f=b;endmodule• Should expand if-else into 4-bit wide multiplexer (a, b, f are 4-bit vectors) and optimize/minimize the control logic:Procedural Assignmentsg• Verilog has two types of assignments within always blocks:• Blocking procedural assignment “=“– RHS is executed and assignment is completed before the next statement is executed; e.g.,Assume A holds the value 1 … A=2; B=A; A is left with 2, B with 2.• Non-blocking procedural assignment “<=“– RHS is executed and assignment takes place at the end of the current time step (not clock cycle); e.g.,Assume A holds the value 1 … A<=2; B<=A; A is left with 2, B with 1.Supported Verilog Constructspp g– Net types: wire, tri, supply1, supply0; register types:reginteger time (64 bit– Procedural assignments: blocking assignments =nonblockingregister types: reg, integer, time (64 bit reg); arrays of reg– Continuous assignments– Gate primitive and module instantiationsassignments =, nonblocking assignments <= (Note: <= cannot be mixed with = for the same register).– Compiler directives: `define, `ifdef, `else`endif`include`undef– always blocks, user tasks, user functions– inputs, outputs, and inouts to a module–All operators (+-*/%<><=>=else, endif, include, undef– Miscellaneous:• Integer ranges and parameter rangesAll operators (+, , , /, %, <, >, <, >, ==, !=, ===, !==, &&, ||, !, ~, &, ~&, |, ~|, ^~, ~^, ^, <<, >>, ?:, { }, {{ }}) [Note: / and % are supported for compile-time constants and constant powers of 2]• Local declarations to begin-end block• Variable indexing of bit vectors on the left and right sides ofconstants and constant powers of 2]– Procedural statements: if-else-if, case, casex, casez, for, repeat, while, forever, begin, end, fork, joinon the left and right sides of assignmentsUnsupported Language Constructspp g gGenerate error and halt synthesis Simply ignored• Net types: trireg, wor, trior, wand, triand, tri0, tri1, and charge strength; • register type: real•Builtin unidirectional and bidirectional• Delay, delay control, and drive strength•