CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDLTajana Simunic Rosing1Source: Eric Crabill, XilinxOverview• Lab #1 due next Wednesday– TA’s extra lab hours posted on webct & course website– Turn in report at the beginning of the class – Wed. 2pm– Demo your work to TA BEFORE Wed. 2pm• What we’ve covered previously:– DelayMux/demux–Mux/demux– Adder• What we’ll be covering next:– Verilog HDL2Hardware description languagespgg• Used to describe & model the operation of digital circuits.• Specify simulation procedure for the circuit and check its response.– Simulation requires a logic simulator.•Synthesis: transformation of theHDL description into a•Synthesis: transformation of the HDL description into a physical implementation (transistors, gates)– When a human does this, it is called logic design.– When a machine does this, it is called synthesis.HDLs• Abel (circa 1983) - developed by Data-I/O– targeted to programmable logic devices– not good for much more than state machines• ISP (circa 1977) - research project at CMU– simulation, but no synthesis• Verilog (circa 1985) - developed by Gateway (absorbed by Cadence)– similar to C– delays are the only interaction with the simulatorfilffi i t d t it–fairly efficient and easy to write– IEEE standard• VHDL (circa 1987) - DoD sponsored standardVHSIC Hardware Description Language–VHSIC Hardware Description Language(VHSIC is Very High Speed Integrated Circuit).– simulation semantics visible; very general but verbose–IEEE standardIEEE standardVerilogUsagegg• Verilog may be used to model circuits and behaviors at various levels of abstraction:• Transistor. LOW• Gate.•Logic.g• Behavioral.• Algorithmic. HIGH• Transistor and gate level modeling is not appropriate for design with FPGA devices.Verilogg• Supports structural and behavioral descriptions• Structural– explicit structure of the circuit– e.g., each logic gate instantiated and connected to othersBehavioral•Behavioral– program describes input/output behavior of circuit– many structural implementations could have same behavior– e.g., different implementation of one Boolean functionStructural modelmodule xor_gate (out, a, b);input a, b;output out;wire abar, bbar, t1, t2;inverter invA (abar, a);inverter invB (bbar, b);and_gate and1 (t1, a, bbar);and_gate and2 (t2, b, abar);or_gate or1 (out, t1, t2);endmoduleBehavioral modelmodule xor_gate (out_or, out_and, a, b);input a, b;output out_or, out_and;reg out_or, out_and;always @(a or b) beginout_or = a ^ b;endassign out_and = a & b;ddlendmoduleData Values• For our logic design purposes, we’ll consider Verilog to have four different bit values:– 0, logic zero.– 1, logic one.z high impedance–z, high impedance.– x, unknown.Data Types and Valuesyp• There are two main data types in Verilog.–Wires.– Regs.• These data types may be single bit or multi-bit.Th l t i {bit idth}’{b }{ l }–The general syntax is: {bit width}’{base}{value} • 4’d14 // 4-bit value, specified in decimal• 4’he // 4-bit value, specified in hex• 4’b1110// 4-bit value, specified in binary• 4’b10xz // 4-bit value, with x and z, in binaryData Typesyp•Wires:–“continuously assigned” values and do not store information.yg– may have multiple drivers assigning values.– When multiple drivers exist, the simulator resolves them into a single value for the wiresingle value for the wire.– Every time a driver changes its output value, the resulting wire value is re-evaluated.This behaves much like an electrical wire•This behaves much like an electrical wire...Data Typesyp• Regs –“procedurally assigned” values that store information until the nextpygvalue assignment is made.– can be used to model combinational or sequential logic.–The name“reg”doesnotmean it is a register!The name reg does notmean it is a register!– A reg may be assigned by multiple processes.– Other reg varieties include integer, real, and time.Modules and Ports• Consider a top level module declaration:module testbench;// Top level modules do not have ports.endmodule• Consider a module declaration with ports:module two_input_xor (in1, in2, out);input in1, in2;p,;output out;// We’ll add more later…endmoduleModules and Ports• Ports may be of type {input, output, inout}and can also be multiple bits wide.pmodule some_random_design (fred, bob, joe, sam, tom, ky);input fred; // 1-bit input portinput [7:0] bob; // 8-bit input portoutput joe; // 1-bit output portoutput [1:0] sam; // 2-bit output portinouttom;// 1-bit bidirectional portinouttom;// 1-bit bidirectional portinout [3:0] ky; // 4-bit bidirectional port// Some design description would be here…gpendmodulePort and Data Typesyp• Input port: –driven from outside the module by a wire or a reg, yg,– inside the module it can only drive a wire• Output port difiidth d lbi–driven from insidethe module by a wire or a reg, – outside the module it can only drive a wire.• Inoutport p– May be driven by a wire, and drive a wire.Instantiationmodule testbench;wire sig3; // wire driven by submoduleregsig1 sig2;//regsassigned bytestbenchregsig1, sig2;// regsassigned by testbenchtwo_input_xor my_xor (.in1(sig1), .in2(sig2), .out(sig3));endmodulemodule two_input_xor (in1, in2, out);input in1, in2;output out;// We’ll add more later…endmoduleendmoduleOperatorsp• Used in both procedural and continuous assignments.•Listed in the order of evaluation precedence:Listed in the order of evaluation precedence:– { } is used for concatenation.Say you have two 1-bit data objects, sam and bob.{sambob} is a 2bit value fromconcatenation{sam, bob} is a 2-bit value from concatenation– {{ }} is used for replication.Say you have a 1-bit data object, ted.{4{t d}} i 4bit l td li tdf ti{4{ted}} is a 4-bit value, ted replicated four times.– Unary operators:! Performs logical negation (test for non-zero).~ Performs bit-wise negation (complements).& Performs unary reduction of logical AND.| Performs unary reduction of logical OR.^ Performs unary reduction of logical XOR.Operators cont.p• Dyadic arithmetic operators (signed and can generate carry out):y)* Multiplication./ Division.% Modulus.%+ Addition.- Subtraction.•Dyadic logical shift operators:•Dyadic logical shift operators:<< Shift