CS 140L Lecture 1OutlinesAdministrationSlide 4Slide 5Slide 6Slide 7Slide 8FPGAs (Field Programmable Gate Arrays)Transistors: SiliconMOS TransistorsTransistors: nMOSTransistors: pMOSTransistor FunctionSlide 15CMOS Gates: NOT GateSlide 17CMOS Gates: NAND GateSlide 19CMOS Gate StructureNOR GateNOR3 GateOther CMOS GatesSlide 24Transmission GatesNoiseThe Static DisciplineLogic LevelsNoise MarginsDC Transfer CharacteristicsSlide 31VDD ScalingLogic Family ExamplesPower ConsumptionDynamic Power ConsumptionStatic Power ConsumptionPower Consumption ExampleSlide 381CS 140L Lecture 1CK ChengCSE Dept.UC San Diego2Outlines•Administration•Lab. Overall View•FPGA Architecture •Transistors•Gates3AdministrationWeb site:http://www.cse.ucsd.edu/classes/sp09/cse140L/WebBoard:http://webboard.ucsd.edu4AdministrationInstructor: CK Cheng, CSE2130, [email protected], 858 534-6184 Teaching Assistants:•Thomas Weng, [email protected] •Renshen Wang, [email protected] •Chengmo Yang, [email protected] •Mingjing Chen, [email protected] •Lecture: 2:00-2:50PM, W, Center 212. •Discussion: 3:00-3:50PM, W, Center 212. •Office hours: 10:30-11:30AM, TTh, CSE 2130.6AdministrationTextbook•Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007. Hardware•Altera DE1 Education KitAdministrationLabs (68%): computer simulations, board demonstration, report write-up. One report per group.•1. Combinational Circuit Designs•2. The Specification and Usage of Flip-Flops•3. Finite State Machines•4. System Design using Datapath and Control SubsystemsFinal (30%): 3:00-4:30PM F6/1278Behavior descriptionC, System C, Verilog, VHDLRegister Transfer LevelVerilog, VHDLNetlist of LogicPhysical LayoutLogic SynthesisPlacement, RoutingMask FabricationFPGAs1. Data Representation 2. Synthesis: Logic, Physical Layout3. Analysis: Functional, Timing VerificationOverall View of Labs9FPGAs (Field Programmable Gate Arrays) Switch MatrixWiring ChannelsProgrammable Logic BlockSwitches-SRAM based (Flash memory)-AntifuseDisadvantages: Penalty on area, density, speedAdvantages: Flexibility, low startup costs, low risk, revisions without changing the hardware10Copyright © 2007 Elsevier1-<10>Transistors: SiliconSilicon LatticeSi SiSiSi SiSiSi SiSiAs SiSiSi SiSiSi SiSiB SiSiSi SiSiSi SiSi-++-Free electronFree holen-Type p-Type•Transistors are built out of silicon, a semiconductor•Pure silicon is a poor conductor (no free charges)•Doped silicon is a good conductor (free charges)–n-type (free negative charges, electrons)–p-type (free positive charges, holes)11Copyright © 2007 Elsevier1-<11>MOS Transistorsnpgatesource drainsubstrateSiO2nMOSPolysiliconngatesource drain•Metal oxide silicon (MOS) transistors: –Polysilicon (used to be metal) gate–Oxide (silicon dioxide) insulator–Doped silicon12Copyright © 2007 Elsevier1-<12>Transistors: nMOSnpgatesource drainsubstraten npgatesource drainsubstratenGNDGNDVDDGND+++++++- - - - - - -channelGate = 0, it is OFF (source and drain are disconnected)Gate = 1, it is ON (channel between source and drain)Source= 0 => Drain=0Source=1 => Drain=0.8 (Poor one)1-<13>Copyright © 2007 Elsevier 1-<13>Transistors: pMOS•pMOS transistor is just the opposite–ON when Gate = 0•Source =0 => Drain = 0.2 (Poor zero)•Source =1 => Drain = 1–OFF when Gate = 1SiO2ngatesource drainPolysiliconp pgatesource drainsubstrate14Copyright © 2007 Elsevier1-<14>Transistor Functiongsdg = 0sdg = 1sdgdsdsdsnMOSpMOSOFFONONOFF15Copyright © 2007 Elsevier1-<15>Transistor Function•nMOS transistors pass good 0’s, so connect source to GND•pMOS transistors pass good 1’s, so connect source to VDDpMOSpull-upnetworkoutputinputsnMOSpull-downnetwork1-<16>Copyright © 2007 Elsevier 1-<16>CMOS Gates: NOT GateVDDA YGNDN1P1NOTY = AA Y0 11 0A YA P1 N1 Y011-<17>Copyright © 2007 Elsevier 1-<17>CMOS Gates: NOT GateVDDA YGNDN1P1NOTY = AA Y0 11 0A YA P1 N1 Y0 ON OFF 11 OFF ON 01-<18>Copyright © 2007 Elsevier 1-<18>CMOS Gates: NAND GateABYN2N1P2 P1NANDY = ABA B Y0 0 10 1 11 0 11 1 0ABYA B P1 P2 N1 N2 Y0 00 11 01 11-<19>Copyright © 2007 Elsevier 1-<19>CMOS Gates: NAND GateABYN2N1P2 P1NANDY = ABA B Y0 0 10 1 11 0 11 1 0ABYA B P1 P2 N1 N2 Y0 0 ON ON OFF OFF 10 1 ON OFF OFF ON 11 0 OFF ON ON OFF 11 1 OFF OFF ON ON 020Copyright © 2007 Elsevier1-<20>CMOS Gate StructurepMOSpull-upnetworkoutputinputsnMOSpull-downnetwork21Copyright © 2007 Elsevier1-<21>NOR GateHow do you build a three-input NOR gate?22Copyright © 2007 Elsevier1-<22>NOR3 GateThree-input NOR gateBCYA23Copyright © 2007 Elsevier1-<23>Other CMOS GatesHow do you build a two-input AND gate?24Copyright © 2007 Elsevier1-<24>Other CMOS GatesTwo-input AND gateABY1-<25>Copyright © 2007 Elsevier 1-<25>Transmission Gates•nMOS pass 1’s poorly•pMOS pass 0’s poorly•Transmission gate is a better switch–passes both 0 and 1 well•When EN = 1, the switch is ON:–EN = 0 and A is connected to B•When EN = 0, the switch is OFF:–A is not connected to BA BENENCopyright © 2007 Elsevier 1-<26>Noise•Anything that degrades the signal–E.g., resistance, power supply noise, coupling to neighboring wires, etc.•Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 voltsDriver ReceiverNoise5 V 4.5 VCopyright © 2007 Elsevier 1-<27>The Static Discipline•Given logically valid inputs, every circuit element must produce logically valid outputs•Discipline ourselves to use limited ranges of voltages to represent discrete valuesCopyright © 2007 Elsevier1-<28>Logic LevelsDriver ReceiverForbiddenZoneNMLNMHInput CharacteristicsOutput CharacteristicsVO HVDDVO LGNDVIHVILLogic HighInput RangeLogic LowInput RangeLogic HighOutput RangeLogic LowOutput RangeCopyright © 2007 Elsevier1-<29>Noise MarginsDriver ReceiverForbiddenZoneNMLNMHInput CharacteristicsOutput CharacteristicsVO HVDDVO LGNDVIHVILLogic HighInput RangeLogic LowInput RangeLogic HighOutput RangeLogic LowOutput RangeNMH = VOH – VIHNML = VIL – VOLCopyright © 2007 Elsevier1-<30>DC Transfer CharacteristicsVDDV(A)V(Y)VOHVDDVOLVIL, VIH0A YVDDV(A)V(Y)VOHVDDVOLVILVIHUnity GainPointsSlope = 10VDD / 2Ideal Buffer: Real Buffer:NMH = NML = VDD/2NMH , NML < VDD/2Copyright © 2007 Elsevier 1-<31>DC Transfer CharacteristicsForbiddenZoneNMLNMHInput CharacteristicsOutput