Implementing Run Time Support for DRAFTS Distributed Real time Applications Fault Tolerant Scheduling Mark McKelvin EE249 Embedded System Design December 03 2002 Mentor Claudio Pinello 1 01 13 19 Outline Objectives Motivation DRAFTS Project Synthesis Design Flow Code Generation 2 Approach Components Work Accomplished Conclusions 01 13 19 Objectives To implement a run time environment that models a real time distributed fault tolerant system code generation To create a library of functions that provides communication services to the system designer To create a library of functions that define an architecture for prototyping 3 01 13 19 Motivation Complex systems are more integrated and often more safety critical Expensive design process Validation of architecture and software integration Repetitive process Expensive implementation 4 Examples A distributed car system and drive by wire applications Late validation of architecture in the design process 01 13 19 DRAFTS Project Automates synthesis from a fault tolerant data flow model of computation to executable code Synthesis based approach 5 Uses a fault tolerant data flow model of computation for safety critical applications Solution approach redundancy for safety and reliability Allows customizable replication of SW and HW Enables fast architecture exploration Handles the complications of redundancy management through code generation debugged and portable libraries 01 13 19 Synthesis Design Flow Application Architecture DRAFTS FTDF library 6 Fault Tolerant Application Code Generation 01 13 19 Code Generation Approach Virtual prototyping tool Designer uses a library of functions to implement communication architecture and placement of actors on the architecture Code created interfaces the FTDF library functionality with a specific architecture Code generation FTDF Library 7 Architecture 01 13 19 Code Generation Components Implemented on a Linux based operating system Consists of multiple Virtual CPUs where each models a single CPU Communication virtual CPUs VCPUs uses UDP IP and virtual channels VCHs which model FTDF communication semantics User Application FTDF Library Code Generation Library VCPU VCPU VCH Linux Operating System UDP IP Physical Network Ethernet 8 01 13 19 Code Generation Work Accomplished 9 Communication library functions implemented that allow designer to specify the number of VCPUs in network Functions that send and receive data between VCPUs A basis for building virtual channels into the virtual architecture Shared memory communication between actors read and write functionality 01 13 19 Conclusions Advantages of code generation Disadvantages of code generation Not a true performance analysis tool Lacks 1 1 mapping of computation to architecture Introduces added overhead Future Work 10 Inexpensive Modular and customizable Designer can introduce redundancy in the virtual network Test complete functionality in an application that uses the FTDF library Implement FTDF semantics in code i e firing rules faults Has potential to be used as a Metropolis back end tool for rapid prototyping of a FTDF network 01 13 19
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