Design Exploration for Wireless Embedded Systems: the Voicemail Pager ExampleWireless Embedded SystemsStarting pointThe Voicemail PagerProtocol LayerSlide 6Protocol SpecificationImplementation ProblemsPhysical LayerOverall Behavior ModelArchitecture ModelsOther ArchitecturesMapping - 1Mapping - 2ResultsConclusionsDesign Exploration for Wireless Embedded Systems: the Voicemail Pager ExampleFernando De BernardinisEE249 Project - Fall 1998Wireless Embedded Systems•Complex designs: Architecture/Functionality/Protocol Hardware/Software/Analog•Complex simulation–Analog effects–Simulation times–Analog/Digital interactions (correc tions)•Protocols map digital functionalities to analog front-ends –Computation load vs. Analog complexity–Flexibility vs. Power and CostStarting point•Design example carried out at UCB and Cadence (a Voicemail pager)•However, not a good high level description for the Felix methodology:–originally carried out in BoNES–few design choices, blackboxes include BoNES files and therefore “hide” functionalities•Two primary objectives:–Re-implement the protocol layer–Include some detail of the modulation schemeThe Voicemail Pager•One-way voice pager system•1 cell only, ~1km radius, industrial site env.•BW requirements: 250Kbps•ISM band 902-928 MHz•FCC requirements–> 50 hop channels, –< 1W max power–< 500 kHz BW/channel (20 dB)–< 0.4 sec hop time•System - level solution so far:–Slow FH system, 50 channels, 50ms hop time–Each hop ch.: 8 ch. FDMA, each ch. 8 TDMA slotsProtocol Layer•Converts bits to frames, i.e. raw bits to control and message data•Analog requirements introduce guard and spacers sections–synchronize receiver at the beginning of frame–separate different messages (TDMA)•Relevant trade-off point: –short frames overhead (control vs. load)–long frames large miss penalty•Therefore: parameterized protocol for optimization purposesProtocol Layer•Several parameters to determine•Guard and Spacers depend on the analog front-end and on the modulation usedGuardHeaderControl SpacersMessagesSuperFrameFrame ProtocolReservedControl 0Control 1Control 2Control 3AddressSF ReferSlotTypeHop offsetLengthReservedMSG0 MSG1 MSG2 MSG3Protocol Specification•Protocol Regular Expression CFSM•Hierarchical CFSMIGuardHeaderCTRLMSGsSpacerISuperFFrameProtocolReservedImplementation Problems•Hierarchy–Felix does not support hierarchical STDs•Loop issues–Self-loop actions imply the increment of an index i and the acquisition of one or more elements h[i] m[i]–There is no way of specifying order in the actions in current implementation of STDs•Therefore, WhiteC models–dynamic delay estimation–less intuitive debuggingPhysical Layer•QPSK modulation•1 Mb/s data rate•Bit level simulation:–Slow simulation time/Accuracy–Separation of testbench from behavior–Better models through SPW (import Dataflow MoC)qpsk modulatormapperdemod_indemod_outqpskdemodulatordmapper_indmapper_outd m a p p e rInO u tin _ d a t ao u t_ fr a m eF r a m e ge n er at o rqpsk modulatormapperWriteVecRealTestbench generatorOverall Behavior ModelVoicemail modelArchitecture Models•10 MHz 16 bit MCU•Pre-emptive static priority RTOS•16 bit/5 MHz busFIFO arbitrated•Interrupt bus tomodel the interaction between the ASIC and th MCU•ASIC to implement the physical layerM Y C P Uc h ildin tr p t _ b u s _ p o r td a ta _ b u s _ p o r tA S I C 1P a g e rR T O SD a tain te rr u p tOther Architectures•Other possibilities: 50 MHz 32 bit MCU–32 bit modeled through the fuzzy instruction set•32 bit/25 MHz busMany blocks in the systems are “blackboxes”, which are provided with a static delay independent of the MCUThis comes from previous BoNES C++ models, and it is quite difficult to extrapolate new delays without having a deep knowledge of each block implementation32 16Mapping - 1•The physical layer is mapped on the ASIC•The protocol model is mapped on software•All remaining blocks are mapped on software•The ASIC/MCU communication is mapped on the Interrupt Bus•Other communications are mapped on the Data BusMapping - 2•Simulation show that the protocol layer cannot be mapped on the MCU–The block is activated at 250kS/s input rate, therefore is not manageable via interrupts–RTOS context switch overhead is 2s •Therefore, the protocol layer is mapped onhardware–estimated delay 0.8 s •The interrupt bus exploit a differentcommunicationResultsConclusions•A parameterized protocol has been created for the voicemail pager and described as a WhiteC block•A basic modulator has been inserted in the physical layer•An architecture has been selected and some mappings were run–Protocol cannot be mapped on software•No further mapping are possible with the “blackbox” description of the system•Some limitations of the current implementation of STDs were pointed
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