SystemC TutorialSystemC IntroductionSystemC is …SystemC EnvironmentSystemC HistorySystemC HistoryObjectives of SystemC 2.0SystemC 2.0 Objectives (cont)Communication and SynchronizationSystemC Language ArchitectureSystemC vs. MetropolisSystem Design MethodologyModeling Terms (I)Modeling Terms (II)Model Types (1)Model Types (2)Current MethodologySystemC MethodologyUsing Executable SpecificationsSystemC and User ModuleSystemC Highlights (1)SystemC Highlights (2)A system in SystemCA system in SystemCSystemC Highlights (3)Data TypesCommunication and Synchronization (cont’d)A Communication Modeling Example: FIFOFIFO Example:Declaration of InterfacesDeclaration of FIFO channelDeclaration of FIFO channel (cont’d)FIFO Example (cont’d)FIFO Example (cont’d)Completing the Comm. Modeling ExampleCompleting the Comm. Modeling Example (cont’d)Completing the Comm. Modeling Example (cont’d)Completing the Comm. Modeling Example (cont’d)SystemC refinementSystemC Channel ReplacementSystemC Adapter InsertionSystemC Adapter MergeSystemC schedulerSystemC & VHDL SimilaritiesSystemC & non DeterminismSystemC Scheduler & EventsSystemC Simulator KernelMetropolis vs. SystemCReferencesSystemC TutorialJohn MoondanosStrategic CAD Labs, INTEL Corp.&GSRC Visiting Fellow, UC BerkeleySystemC Introduction Why not leverage experience of C/C++ developers for H/W & System Level Design? But C/C++ have no notion of time No event sequencing Concurrency But H/W is inherently concurrent H/W Data Types No ‘Z’ value for tri-state busesSystemC is … C++ Class Library use for Cycle-Accurate model for Software Algorithm Hardware Architecture Interface of SoC (System-on-Chip) System-level designs Executable Specification www.systemc.orgSystemC EnvironmentSystemC History SystemC 1.0 Provide VHDL like capabilities Simulation kernel Fixed point arithmetic data types Signals (communication channels) Modules Break down designs into smaller partsSystemC History SystemC 2.0 Complete library rewrite to upgrade into true SLDL Events as primitive behavior triggers Channels, Interfaces and Ports Much more powerful modeling for Transaction Level Future SystemC 3.0 Modeling of OSs Support of embedded S/W modelsObjectives of SystemC 2.0 Primary goal: Enable System-Level Modeling Systems include hardware and software Challenge: Wide range of design models of computation Wide range of design abstraction levels Wide range of design methodologiesSystemC 2.0 Objectives (cont) SystemC 2.0 Introduces a small but very general purpose modeling foundation => Core Language Support for other models of computation, methodologies, etc They are built on top of the core language, hence are separate from it Even SystemC 1.0 Signals are built on top of this core in SystemC 2.0 Other library models are provided: FIFO, Timers, ...Communication and Synchronization SystemC 1.0 Modules and Processes are still useful in system design But communication and synchronization mechanisms in SystemC 1.0 (Signals) are restrictive for system-level modeling Communication using queues Synchronization (access to shared data) using mutexesSystemC Language ArchitectureCore SystemSystemC vs. Metropolis Constructs to model system architecture Hardware timing Concurrency Structure Adding these constructs to C SystemC C++ Class library Standard C/C++ Compiler : bcc, msvc, gcc, etc… Metropolis New keywords & Syntax Translator for SystemC Many More features…System Design Methodology Current Manual Conversion from C to HDL Creates Errors Disconnect Between System Model and HDL Model Multiple System Tests SystemC (Executable-Specification) Refinement Methodology Written in a Single LanguageModeling Terms (I) Untimed Functional (UTF) Refers to model I/F and functionality No time used for regulating the execution Execution & data transport in 0 time Timed Functional (TF) Refers to both model I/F and functionality Time is used for the execution Latencies are modeled Data Transport takes timeModeling Terms (II) Bus Cycle Accurate (BCA) Refers to model I/F, not functionality Timing is cycle accurate, tied to some global clock Does not infer pin level detail Transactions for data transport Pin Cycle Accurate (PCA) Refers to model I/F not model functionality Timing is cycle accurate Accuracy of the I/F at the pin Level Register Transfer (RT) Accurate Refers to model functionality Everything fully timed Complete detailed Description, every bus, every bit is modeledModel Types (1) System Architectural Executable specification for H/W & S/W Architecture Exploration, algorithm determination & proof I/Fs are UTF with no pin detail for modeling communication protocols Functionality UTF, sequential since it’s untimed System Performance Timed executable specification for bith H/W & S/W Used for time budgeting Concurrent behavior modeled Transaction Level (TLM) Typically describe H/W only Model I/Fs are TF, functionality TF as well (either not cycle accurate) Data Transfers & system Behavior modeled as transactionsModel Types (2) Functional Model Above TLM, i.e. System Architectural & System Performance System Level Above RTL Behavioral Synthesis Architectural Analysis & Implementation I/F cycle accurate with pin level detail Functionality TF and not cycle accurate Bus Functional Model (BFM) Used for simulation (mainly of processors) Not meant for synthesis I/F pin cycle accurate Transactions for functionality Register Transfer Level (RTL) Verilog, VHDL Gate Level not good in SystemCCurrent MethodologyC/C++System Level ModelAnalysisResultRefineVHDL/VerilogSimulationSynthesis- Manual Conversion Creates Errors- Disconnect Between System Model and HDL Model- Multiple System TestsSystemC MethodologyUsing Executable Specifications Ensure COMPLETENESS of Specification“Create a program that Behave the same way as the system” UNAMBIGUOUS Interpretation of the Specification Validate system functionality before implementation Create early model and Validate system performance Refine and Test the implementation of the SpecificationSystemC and User ModuleExecutable SpecificationExecutable
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