The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 The Essence of Polis Felix VCC Project Virtual Component CoCo design The next level of Abstraction IP Block Performance Inter IP Communication Performance Models 1988 Describe product architectures Explore HW SW design tradeoffs s s s Map behavior to architecture Use performance simulation Perform communication refinement Integrated flow to implementation Behavior Simulation RTL Gate Level Model Capacity Load Mapping Transistor Model Capacity Load 3 Performance Simulation Communication Refinement 4 abstract Describe verify product behavior 2 System Architecture cluster RTL Clusters SW Models cluster abstract System Behavior abstract 1 abstract SDF Wire Load IP Blocks cluster Flow To Implementation 1 Page 1 1970 s 1980 s 1990 s Year 2000 2 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 OMAP Block Diagram Architectural Choices Program Memory SDRAM Flexibility Prog Mem Prog Mem P Prog Mem Satellite Dedicated Logic P Processor Satellite Satellite Processor Processor MAC Unit Addr Gen Memory Traffic Controller P uARM9 core uC55x DSP core I MMU General Purpose P u16KB I cache Software Programmable DSP u8KB DD cache D MMU MMU I Cache D Cache RISC Core associative Direct Mapped Hardware u150 MHz u16KB I cache DSP Core u8KB RAM set Appl Coprocessors u2 way set Hardware Reconfigurable Processor Internal I Cache RAM ROM DMA Peripherals u2 way set associative LCD Controller Interrupt Handlers Timers GPIO UARTs u200 MHz 1 Efficiency power speed 3 Page 2 4 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 Hardware Platforms Not Enough uHardware platform has to be abstracted uInterface to the application software is the API uSoftware layer performs abstraction 5 Page 3 s Programmable cores and memory subsystem hidden by RTOS and compilers s I O subsystem with Device Drivers s Network with Network Communication Software 6 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 Nexperia DVP Software Nexperia Software Platforms uNexperia Nexperia Platform API Application Software Middleware JavaTV TVPAK OpenTV MHP Java proprietary Software Software Platform Hardware Platform Input devices Output Devices Hardware I O Compiler RTOS API Device Drivers BIOS Network Communication network Streaming and Platform Software Kernel pSOS Win CE JavaOS Applications DVP Software Architecture s Supports multiple OSs and middleware software s Abstracts platform functionality via consistent APIs uNexperia Nexperia DVP s uNexperia Nexperia s Streaming Software Encapsulates implementation of streaming media components hardware and software Platform Software OS independent device drivers for ononchip and offoff chip devices Nexperia Hardware 7 Page 4 8 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 MOSAIC SW Architecture Components for Automotive Dashboard and Body Control Platforms Application Space Application Application Platform Platform layer layer 10 10 of of total total SW SW Application Instance Application Libraries Customer Libraries Platform Specification CCP Water temp Odometer Tachometer Tachometer Speedometer Speedometer SW SW Platform Platform layer layer 60 60 of of total total SW SW OSEK RTOS KWP 2000 Application Specific Software Application Programming Interface Sys Config Transport OSEK COM I O drivers handlers 20 configurable modules SW SW Platform Platform Reuse Reuse 70 70 of of total total SW SW System Platform Platform Design Space Exploration Boot Loader Controllers Library HW HW layer layer Nec78k Nec78k HC08 HC08 HC12 HC12 H8S26 H8S26 Platform Instance Architectural Space MB90 MB90 9 Page 5 10 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 Platforms Platforms uA platform is in general an abstraction that covers a number of possible refinements into a lower level For every platform there is a view that is used to map the upper layers of abstraction into the platform and a view Platform stack that is used to define the class of lower level abstractions Platform Mapping Tools Platform implied by the platform 11 Page 6 12 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 Application example Power Train Control System Power u Automotive PowerPower Train Control Design from car manufacturer u Electronic device controlling an internal combustion engine and a gearbox u The goal specs to software design to architecture selection to IC implementation u Project in collaboration with Cadence MagnetiMagneti Marelli ST u Microelectronics Accent u s offer appropriate driving performance e g torque comfort safety safety s minimize fuel consumption and emissions Relevant characteristics s strictly coupled with mechanical parts s hard real time constraints s complex algorithms for controlling fuel injection spark ignition ignition throttle position gear shift s 135 000 lines of C code with no comments First Step was to rere design software with methodology to map into different hardware platforms with little effort 13 Page 7 14 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 INPUTS System Specifications KGT B C Stop Key Gas Pedal Clutch Pedal Gear Stick Brake Pedal Cruise Control FG 0 n n min K O f f G 0 FG 0 n a r g m i n M fuel G 0 F G 0 Comfort n n G FG 0 T 0 T 0 Fast Negative Force Transient max D max F G F G G T n f I n 0 G 0 G 0 t Force Tracking G 0 t min f D M f u e l G GB B 1 G 0 B 1 Speed Tracking Page 8 D Rpm Tracking G 0 T 0 T 0 15 n n startup G 0 G 0 Idle T 0 T 0 n Engine Speed F G Generated Force V G Vehicle Speed n n n m i n K O f f T 0 G 0 OUTPUT Startup K Start n 0 V G V G m a x F G F G G T n min G GA f I n 0 G 0 G 0 C 1 Fast Positive Force Transient M fuel M m a x D D m i n F G F G G T n fI n G 0 Idle Trasm O n n n T 0 16 The MARCO DARPA Gigascale Silicon Research Center for Design Test Form Executive Advisory Group Review 23 September 1999 Goal Model of PowerPower train uDevelop guaranteed properties control algorithms for all Throttle opening angle power train modes power
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