Page 1The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 199911ŒŒ Describe & verify product behaviorDescribe & verify product behavior•• Describe product architecturesDescribe product architecturesŽŽ Explore HW/SW design tradeoffsExplore HW/SW design tradeoffsss Map behavior to architectureMap behavior to architecturess Use performance simulationUse performance simulationss Perform communication refinementPerform communication refinement•• Integrated flow to implementation Integrated flow to implementation SystemSystemBehaviorBehaviorSystemSystemArchitectureArchitectureMappingMappingFlow To ImplementationFlow To ImplementationCommunicationRefinementBehaviorBehaviorSimulationSimulationPerformancePerformanceSimulationSimulation2134The Essence of Polis/Felix/VCC Project: Virtual The Essence of Polis/Felix/VCC Project: Virtual Component CoComponent Co--designdesign1988:1988:22TheThe next level of Abstraction …next level of Abstraction …abstractTransistor ModelCapacity Load1970’sclusterabstractGate Level ModelCapacity Load1980’sRTLclusterabstractSDFWire Load1990’sIP BlocksclusterabstractIP Block PerformanceInter IP Communication Performance ModelsRTLClustersSWModelsYear 2000 +Page 2The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 199933Architectural ChoicesArchitectural ChoicesµPProg MemMACUnitAddrGenµPProg MemµPProg MemSatelliteProcessorDedicatedLogicSatelliteProcessorSatelliteProcessorGeneralPurposeµPSoftwareDirectMappedHardwareHardwareReconfigurableProcessorProgrammableDSPFlexibilityFlexibility1/Efficiency (power, speed)1/Efficiency (power, speed)44OMAP™ Block DiagramOMAP™ Block DiagramI-MMU D-MMUI-CacheRISC CoreMMUI-CacheInternal RAM/ROMDSP Core+ Appl Coprocessors DMAMemory & Traffic ControllerProgramMemorySDRAMPeripheralsLCD Controller, Interrupt Handlers, Timers, GPIO, UARTs, ...uuARM9 coreARM9 coreuu16KB I16KB I --cachecacheuu8KB D8KB D--cachecacheuu22--way set way set associativeassociativeuu150 MHz150 MHzuuC55x DSP coreC55x DSP coreuu16KB I16KB I --cachecacheuu8KB RAM set8KB RAM setuu22--way set way set associativeassociativeuu200 MHz200 MHzD-CachePage 3The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 199955 66Hardware Platforms Not Enough!Hardware Platforms Not Enough!uuHardware platform Hardware platform has to be abstractedhas to be abstracteduuInterface to the application software is the Interface to the application software is the “API”“API”uuSoftware layer performs abstraction:Software layer performs abstraction:ss Programmable cores and memory subsystem “hidden” Programmable cores and memory subsystem “hidden” by RTOS and compilersby RTOS and compilersss I/O subsystem with Device DriversI/O subsystem with Device Driversss Network with Network Communication SoftwareNetwork with Network Communication SoftwarePage 4The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 199977Software PlatformsSoftware PlatformsOutput DevicesInput devicesHardware PlatformI OHardwareSoftwarenetworkSoftware PlatformApplication SoftwarePlatform APIAPIRTOSBIOSDevice DriversNetworkCommunicationCompiler88MiddlewareJavaTV, TVPAK, OpenTV, MHP/Java, proprietary ...ApplicationsNexperiaNexperia HardwareHardwareStreaming andStreaming andPlatform SoftwarePlatform SoftwareKernel: pSOS, Win-CE, JavaOSNexperiaNexperia--DVP SoftwareDVP SoftwareuuNexperiaNexperia™ ™ --DVP Software ArchitectureDVP Software Architecturess Supports multiple Supports multiple OSsOSs and and middleware softwaremiddleware softwaress Abstracts platform functionality via Abstracts platform functionality via consistent APIsconsistent APIsuuNexperiaNexperia™™--DVP Streaming SoftwareDVP Streaming Softwaress Encapsulates implementation of Encapsulates implementation of streaming media components streaming media components (hardware and software)(hardware and software)uuNexperiaNexperia™ Platform Software™ Platform Softwaress OS independent device drivers for onOS independent device drivers for on--chip and offchip and off--chip deviceschip devicesPage 5The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 199999HW layerHW layerSW Platform layer(> 60% of total SW)SW Platform layerSW Platform layer(> 60% of total SW)(> 60% of total SW)Application Platform layer(≅ 10% of total SW)Application Platform layerApplication Platform layer((≅ ≅ 10% of total SW)10% of total SW)µControllers LibraryOSEKRTOSOSEKCOMI/O drivers & handlers(> 20 configurable modules)Application Programming InterfaceBoot LoaderSys. Config.TransportKWP 2000CCPApplicationSpecificSoftwareSpeedometerTachometerWater temp.SpeedometerTachometerOdometer---------------ApplicationLibrariesNec78kNec78k HC12HC12HC08HC08H8S26H8S26MB90MB90SW Platform Reuse> 70%of total SWSW SW Platform Platform ReuseReuse> 70%> 70%of total SWof total SWCustomerLibrariesMOSAIC SW Architecture & Components for Automotive Dashboard and Body Control1010PlatformsPlatformsPlatformDesign -SpaceExplorationPlatformSpecificationArchitectural SpaceApplication SpaceApplication InstancePlatform InstanceSystemPlatformPage 6The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 19991111PlatformsPlatformsuuA platform is, in general, an abstraction that covers a A platform is, in general, an abstraction that covers a number of possible refinements into a lower level. number of possible refinements into a lower level. For For every platform, there is a view that is used to map the every platform, there is a view that is used to map the upper layers of abstraction into the platform and a view upper layers of abstraction into the platform and a view that is used to define the class of lower level abstractions that is used to define the class of lower level abstractions implied by the platform. implied by the platform. 1212PlatformsPlatformsPlatformMapping ToolsPlatformPlatform stack{Page 7The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: FormExecutive Advisory Group Review23 September 19991313ApplicationApplication example:example:uuAutomotive PowerAutomotive Power--Train Control Design: from car manufacturer Train Control Design: from car manufacturer specs
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