A Methodology for Architecture Exploration of heterogeneous Signal Processing SystemsOutlineProblem DefinitionProblem Definition cont’dRelated WorkBasic PrinciplesBasic Principles cont’dSPADESPADE cont’dSlide 10Slide 11Case Study: An MPEG-2 DecoderConclusionA Methodology for Architecture Exploration of heterogeneous Signal Processing SystemsPaul Lieverse, Pieter van der Wolf, Ed Deprettere, Kees VissersOutlineProblem definitionRelated workBasic principlesMethodology SPADECase studyConclusionProblem DefinitionModern signal processing systems have a heterogeneous architecture:programmable components to offer various functions and support different standards for transmission, dedicated hardware blocks for cost and power consideration.New design Methodology SPADE for architecture exploration of heterogeneous signal processing systems Starts from a set of target applications Results in the definition of an architecture capable of executing the applications within predefined constraintsProblem Definition cont’dThe design has to start with abstract yet executable models.Cost of model construction and model evaluationFlexibility to explore alternative architecturesRelated WorkApplication modeling: Models of computationSynchronous Dataflow(SDF), Dataflow Process Networks, Kahn Process Networks.Architecture modeling and performance analysis at system levelPolis, reactive systemsChinook, embedded systemsRASSP, DSP systemsQuantitative analysis of architectures, by A.C.J.Kienhuis, limited to a specific class of dataflow architecturesIn contrast, SPADE distinguishes between application models and architecture models, and supports explicit mapping reusabilityBasic Principles The Y-Chart: a general scheme for the design of programmable architecturesBasic Principles cont’dWorkload and ResourcesComputation, communication workloadProcessing, communication, memory resources, etcApplications and architectures are modeled separatelyTrace-Driven Simulation: performance analysisApplications: network of concurrent communicating processesTrace: workloadSPADE Application ModelingObjective: expose parallelism, make communication explicit Kahn Process NetworksThe execution is deterministicIt fits nicely with signal processing applicationsIt allows programmers to easily combine communication primitives with control constructsApplication Programmers Interface (API) of SPADERead functionWrite functionExecution function, to handle symbolic instructionTrace entries are generated by them.SPADE cont’dArchitecture ModelingEasy to construct. No need to model the functional behaviorLibrary of Generic building blocks, which are parameterizedTrace driven execution unit (TDEU), which interprets trace entriesInterfaces, which connects the I/O ports of TDEU to communication resourceGeneric bus blockSPADE cont’dMapping. Each process is mapped onto a TDEU. Can be many-to-one, but not one-to-manyEach process port is mapped one-to-one onto an I/O portSPADE cont’dSimulationConcurrently simulate the application model and the architecture model in a single memory spacePerformance MetricsThe building blocks contain collectors for performance metrics. Data is collected during simulation.Case Study: An MPEG-2 Decoder Starts with the C-code of the MPEG-2 video decoder Step 1: partition the sequential program into a parallel Kahn Process Network using API functionsStep 2: Collect statistics of the workload for different MPEG sequences, by running the application in stand-alone modeStep 3: construct model for a realistic architecture, TM-2700 MPEG architecture, using the blocks from the libraryStep 4: Define a mappingStep 5: Perform simulation. Identify the bottlenecks.ConclusionSPADE supports efficient exploration of heterogeneous signal processing architectures that must satisfy the workload demands of multiple target applicationsKahn API functions can be used to structure applicationsA broad class of architectures can be modeled with the generic architecture blocks from the libraryTrace-driven simulation is used for co-simulation. Simulation speed, about 20,000 cycles per second for a relatively complex design. A number of architectures and mappings can be
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