Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design1M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli University of California at Berkeley, Princeton University {sgroi, msheets, mihal, keutzer, jan, alberto}@eecs.berkeley.edu; [email protected] ABSTRACT Communication-based design represents a formal approach to system-on-a-chip design that considers communication between components as important as the computations they perform. Our “network-on-chip” approach partitions the communication into layers to maximize reuse and provide a programmer with an abstraction of the underlying communication framework. This layered approach is cast in the structure advocated by the OSI Reference Model and is demonstrated with a reconfigurable DSP example. The Metropolis methodology of deriving layers through a sequence of adaptation steps between incompatible behaviors is illustrated through the Intercom design example. In another approach, MESCAL provides a designer with tools for a correct-by-construction protocol stack. GENERAL TERMS—Design KEYWORDS—Network-on-chip; platform-based design; communication-based design; protocol stack. 1. INTRODUCTION It is now not only possible, but also economical, to integrate complex systems on a single silicon die. Designing such systems on a chip (SOC) is a complex process, and is currently approached with little organizing principles. The Gigascale Silicon Research Center (GSRC) aims to provide the essential tools and methodologies to allow integrated circuit designers to make the transition from ad hoc SOC design to a disciplined platform-based design. Essential elements of platform-based design are the design of the computation, i.e. the functional behavior of each core, and communication, i.e. its interaction between the cores. This orthogonalization of concerns is essential to the success of a re-use strategy as has been realized in recent years. The platform-based design methodology [9] addresses this concern by placing the computational cores and their interconnect strategy on the same footing. As was learned by the telecommunications community a while ago, reliable communication between components requires the definition of a protocol that provides a set of rules dictating how the interaction among components takes place, so that the overall system communication and performance requirements are met, while physical resources such as area and energy are minimized. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet the challenges posed by next-generation SOC designs, namely: • Predictability - The capability of making early decisions based on the expected performance of the final implementation is very important in communication design to avoid time-consuming design iterations. The shift towards deep-sub-micron integration makes this aspect even more critical. The increasing ratio of the delay of long wires with respect to gate delay and the dependence of the propagation delay on the chip topology makes it increasingly hard to have the system functionality rely on physical parameters only. • Wiring delay - SOCs that occupy a large area and require long wires to connect communicating components face relevant delay and synchronization problems, especially if multiple (potentially asynchronous) clock domains are used. • Power dissipation - The power consumed by the interconnect structures, including clocks, is rapidly becoming a dominant component of the overall power-budget. • Diverse interconnect architectures – In the past the choice of the interconnect architecture was limited to a few choices, given the small number of blocks that had to be interconnected and the relative simplicity in dominating the performance and delay trade-offs. For SOCs, a richer set of interconnect schema should be examined: for example, shared communication resources such as busses, crossbars, and meshes to minimize resource needs. Solving the latency vs. throughput tradeoff now requires to take in consideration a large number of design parameters, like pipeline stages, arbitration, synchronization, routing and repeating schemes. To address these challenges it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable while not restricting the design space at the same time. Communication design has to begin at higher levels of abstraction than the architecture and RTL level. We believe that a layered approach similar to that defined by the communication networks community (and standardized as the ISO-OSI Reference Model (RM) [18]) to address the problem of connecting a large number of computers on wide-area networks should also be used for on-chip communication design. The layered approach is well suited to describe protocol functions that operate on data units at different levels of abstraction (in the form of streams, packets, bits or analog waveforms) and that are subject to various time granularity constraints. Each layer may include one or more closely related protocol functions, such as data fragmentation, encoding and synchronization. Separating the communication protocol functions into layers that interact only via well-defined interfaces allows for a decomposition of the design problem into a set of simpler, tractable problems, and 1 This research is sponsored in part by the Marco GSRC center, DARPA-ITO and CNR. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2001, June 18-22, 2001, Las Vegas, Nevada, USA. Copyright 2001 ACM 1-58113-297-2/01/0006…$5.00.simplifies the synthesis and validation tasks. As amply demonstrated in the communication-network domain, the approach also maximizes re-use. An excellent example in case is the 802.11 wireless local-area network standard, where a single media-access layer supports different physical implementations through a unified interface. We call the layered-stack approach to the design of the on-chip inter-core communications
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