Welcome to EE249: Embedded System Design The Real StoryAdministrationGradingDiscussion sectionsPlanCourse overviewBehavior Vs. ArchitectureBehavior Vs. CommunicationOutline of the courseIntroduction OutlineElectronics and the CarInformation Technology ScenarioHistoric PerspectiveWhat’s Important: Shifts in Technology MetricsWhat’s Important: Shifts in User/Applications MetricsOutlineChips Everywhere!Smart DustSmart Dust ComponentsAirborne DustSynthetic Insects R. Yeh, K. Pister, UCB/BSACComputing Revolution: Devices in the eXtremeModern Vehicles, an Electronic SystemVehicles, a Consumer Electronic SystemWhen Will Dick Tracy’s Watch Be Available?Smart BuildingsHome Networking: Application (Subnet) ClustersSilicon-Processed Micro-needlesIndustrial Structure ShiftProductivity GapThe Berkeley Wireless Research Center (BWRC)The “Universal” RadioUltra Low-Power PicoRadioIntegrated CMOS RadioCommunication versus ComputationEnergy-efficient Programmable Implementation PlatformSlide 37What is Needed? (Endeavor Expedition,Berkeley, Oxygen, MIT)Technology Changes & Architectural ImplicationsAdaptive Self-ConfigurationLoose OrganizationAny-to-Any TransducersNext-Generation Operating EnvironmentsSlide 44What is a System Anyway?System (for us)Embedded SystemsElectronic System Design Landscape: The Automotive CaseDisaggregation: Complex Design Chain ManagementSupply Chain: Design Roles-> Methodology->ToolsAutomotive Supply Chain: Car ManufacturersAutomotive Supply Chain: Subsystem ProvidersSlide 54Automotive Supply Chain: Platform & IP ProvidersIssues Limiting SOC RampSoC Landscape 2000+Productivity 2000+ ChallengeProcess Challenge Can you integrate what you need ?Slide 60Deep Submicron Paradigm ShiftImplementation Design TrendsDigital Wireless PlatformWill the system solution match the original system spec?EDA Challenge to Close the Gap (SIA MARCO GSRC Project, Berkeley Center)Welcome to Welcome to EE249: EE249: Embedded Embedded System DesignSystem DesignThe Real StoryThe Real StoryAlberto Sangiovanni-VincentelliAlberto Sangiovanni-VincentelliDepartment of EECS, University of California at Department of EECS, University of California at BerkeleyBerkeley2AdministrationAdministrationOffice hours: Office hours: Alberto’s : Tu-Th 12:30pm-2pm or (better) by Alberto’s : Tu-Th 12:30pm-2pm or (better) by appointment (2-4882)appointment (2-4882)Teaching Assistant: Teaching Assistant: Rong ChenRong Chen, [email protected], [email protected]Grading will be assigned on:Grading will be assigned on:Homeworks (~30%) Homeworks (~30%) Project (~50%)Project (~50%)Reading assignments (~20%)Reading assignments (~20%)There will be approx. 7 homeworks (due 2 weeks after There will be approx. 7 homeworks (due 2 weeks after assignment) and 6 reading assignmentsassignment) and 6 reading assignments4Discussion sectionsDiscussion sectionsLab section (Th. 4-6):Lab section (Th. 4-6):tool presentationstool presentationsDiscussion Session (Tu. 5-6)Discussion Session (Tu. 5-6)students’ presentation students’ presentation of selected papersof selected papersEach student will have Each student will have to turn in a one-paragraph report to turn in a one-paragraph report for each for each paper handed outpaper handed outEach student (in groups of 2-3 Each student (in groups of 2-3 people) will have to make an oral people) will have to make an oral presentation once during the presentation once during the classclassAuditors are OK but please Auditors are OK but please register as P-NPregister as P-NPWeek Lab Sections Homeworks1 - - - - - -2 Tool presentation HW13 Discussion4 Tool presentation HW25 Discussion6 Tool presentation HW37 Discussion8 Tool presentation HW49 Discussion10 Tool presentation HW511 Discussion12 Tool presentation HW613 Discussion14 HW7155PlanPlanWe are on the edge of a revolution in the way electronics products are We are on the edge of a revolution in the way electronics products are designeddesignedSystem design is the keySystem design is the keyStart with the highest possible level of abstraction (e.g. control algorithms)Start with the highest possible level of abstraction (e.g. control algorithms)Establish properties at the right levelEstablish properties at the right levelUse formal modelsUse formal modelsLeverage multiple “scientific” disciplinesLeverage multiple “scientific” disciplinesEstablish horizontal and vertical “supplier-chain” like partnershipsEstablish horizontal and vertical “supplier-chain” like partnershipsNeed change in educationNeed change in education6Course overviewCourse overviewManaging ComplexityOrthogonalizing concernsBehavior Vs. ArchitectureComputation Vs. Communication7Behavior Vs. ArchitectureBehavior Vs. ArchitectureSystemSystemBehaviorBehaviorSystemSystemArchitectureArchitectureMappingMappingFlow To ImplementationFlow To ImplementationCommunicationRefinementBehaviorBehaviorSimulationSimulationPerformancePerformanceSimulationSimulation1342Models of ComputationPerformance models: Emb. SW, comm. and comp. resourcesHW/SW partitioning,SchedulingSynthesisSW estimation8Behavior Vs. CommunicationBehavior Vs. CommunicationClear separation between functionality and interaction Clear separation between functionality and interaction modelmodelMaximize reuse in different environments, change only Maximize reuse in different environments, change only interaction modelinteraction modelETROPOLISPIG: Protocol interface generationPEARLS: Latency insensitive protocols9Outline of the courseOutline of the coursePart 1. Introduction: Future of Information Technology, Part 1. Introduction: Future of Information Technology, System Design, IP-based Design, System-on-Chip and System Design, IP-based Design, System-on-Chip and Industrial TrendsIndustrial TrendsPart 2. Design Methodology (Platform-based Design, Part 2. Design Methodology (Platform-based Design, Communication-based Design)Communication-based Design)Part 3. Functional Design: Models of ComputationPart 3. Functional Design: Models of ComputationPart 4. Architecture Design: Capture, Exploration and MappingPart 4. Architecture Design: Capture, Exploration and MappingPart 5. Implementation Verification and
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