Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc UCB November 8 2001 Krishna V Palem Proceler Inc 2 Designing Instruction Sets Choice of instructions is determined by several trade offs Implementation in a fixed silicon area Ability of the compiler to exploit its presence Trade off between impact on cycle time vs frequency Implementation cost is amortized across many applications Infeasible to tailor support for a small number of low volume applications Reconfigurable logic enables a new degree of freedom UCB November 8 2001 Krishna V Palem Proceler Inc Dynamically Variable Instruction Set Architecture DVAITA C P Software engineer C programming Algorithm Design Off line Construction Fundamentally alters the hardware software interface Compiler Fixed ISA DVAITA ISA UCB November 8 2001 Reconfigurable Logic Synthesis Map Place Application specific Soft Processor Microprocessor core 3 Soft Micro architecture Components Krishna V Palem Proceler Inc 4 DVAITA DVAITA is a soft ISA Pre synthesized pre placed instruction implementations DVAITA compiler Analysis program transformation and scheduling algorithms Compilation to a domain specific ISA Create a customized micro architecture at compile time DVAITA Hardware Support Package Analogy with Board Support Packages BSP Run time for host FPGA communication Abstraction for linking the supporting hardware software interfaces UCB November 8 2001 Krishna V Palem Proceler Inc 5 DVAITA Enabled Customization Customization at the domain level Soft ISAs for DSP Telecommunications Industrial automation and control etc Customization at the program level Tailored micro architecture produced at compile time Customization at the operation level Tailored arithmetic and logic operations for example power vs speed UCB November 8 2001 Krishna V Palem Proceler Inc Compiling Code Segments to Hardware L1 for L2 for L3 for L4 for L5 for UCB November 8 2001 DVAITA ISA DVAITA ISA Datapath Control Memory I O Interfaces Datapath Control Memory I O Interfaces Krishna V Palem Proceler Inc 6 Compile time generation of Application specific soft processors 7 ISAs can be selected on a domain specific basis UCB November 8 2001 Krishna V Palem Proceler Inc Application Specific Soft Processors Software Engineer CP C Programming Algorithm Design Application specific soft processors Reconfigurable Computing System RCS Microprocessor core Reconfigurable Logic UCB November 8 2001 Communicatio n Compiler Soft Microarchitecture Components Networkin g Security Krishna V Palem Proceler Inc 8 9 Commercial Hardware Platforms High end System on a Chip solutions Xilinx Virtex 2 with embedded PPC 405 Altera Excalibur with embedded ARM Low end System on a Chip solutions Triscend Configurable System on a Chip CSoC with embedded ARM Atmel Field Programmable System Level Integrated Circuits FPSLIC with embedded 8 bit custom RISC processor Board level products Mix embedded processors and commercial FPGA solutions UCB November 8 2001 Krishna V Palem Proceler Inc 10 More Generally Architecture Assembly Applications An ISA view Synthesis and other hardware design off line Build off line synthesis place and route Program Compiler selects assembles Much closer to compiler and optimizes program optimizations implies faster compile time Data path Prebuilt Implementations Storage Interconnect Dynamically variable ISA Architecture implementation UCB November 8 2001 Also applicable to yield fixed implementations in silicon Krishna V Palem Proceler Inc 11 Placing in Perspective UCB November 8 2001 Krishna V Palem Proceler Inc The Space for these Technologies 12 ASIC Designed with EDA Tools PICO Performance CMP NP Software programmable CMP Custom Microprocessor COTS PROCESSOR NP Network processor Speed to market UCB November 8 2001 Krishna V Palem Proceler Inc
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