Challenges Shift to Reuse Strategy Higher Level of Abstractions Software 1 PERCENT OF TRANSISTORS WITHIN EMBEDDED IP EXCLUDES MEMORY 100 Transistors Random Logic Transistors Transistors Within Embedded IP 5 Year 1997 1998 1999 2000 2001 2002 2003 2004 2005 Feature Dimension m 0 35 0 25 0 18 0 15 0 13 0 11 0 10 0 08 0 07 2 TRENDS IN EMBEDDED IP 1998 1999 2000 2001 2002 2003 2004 2005 2006 112 005 133 426 174 723 164 592 173 506 197 118 227 752 269 078 313 214 NA 19 1 31 0 5 4 13 6 15 5 18 1 16 4 43 506 50 493 64 366 67 581 76 034 92 804 115 123 145 700 175 767 NA 16 1 27 5 5 0 12 5 22 1 24 0 26 6 20 6 Percent total 38 8 37 8 36 8 41 1 43 8 47 1 50 5 54 1 56 1 IP based design Value M 15 706 19 894 30 123 39 129 51 247 68 582 90 602 122 679 153 093 NA 26 7 51 4 29 9 31 0 33 8 32 1 35 4 24 8 36 1 39 4 46 8 57 9 67 4 73 9 78 7 84 2 87 1 Total IC Value M Growth rate System IC Value M Growth rate Growth rate 400 Percent sys tem IC 5 8 350 DESIGNS WITH EMBEDDED IP WILL DOMINATE THE SYSTEM IC BUSINESS IN THE FUTURE 300 Value B 250 IC Market 200 150 100 Designs With Embedded IP 50 0 1998 1999 2000 2001 2002 2003 2004 2005 System IC Market 2006 Year 3 Intra and Inter Company World Wide IP Networks System House Corporate Headquarters Rapid IP Identification Business Transaction Design in Overseas Affiliate with Proprietary IP Semiconductor IP Provider Independent IP Provider 12 09 1999 4 Image borrowed from an Iomega advertisement for Y2K software and disk drives Scientifc American September 1999 Computing for Embedded Systems 5 Complexity Quality Time to Market TODAY PWT UNIT BODY GATEWAY INSTRUMENT CLUSTER TELEMATIC UNIT MEMORY 256 KB 128 KB 184 KB 8 MB LINES OF CODE 50 000 30 000 45 000 300 000 PRODUCTIVITY 6 LINES DAY 10 LINES DAY 6 LINES DAY 10 LINES DAY 3000 PPM 2500 PPM 2000PPM 1000 PPM CHANGING RATE 3 YEARS 2 YEARS 1 YEAR 1 YEAR DEV EFFORT 40 MAN YEAR 12 MAN YEAR 30 MAN YEAR 200 MAN YEAR VALIDATION TIME 5 MONTHS 1 MONTH 2 MONTHS 2 MONTHS TIME TO MARKET 24 MONTHS 18 MONTHS 12 MONTHS 12 MONTHS RESIDUAL DEFECT RATE END OF DEV C CODE Source EMBEDDED SYSTEMS THE REAL STORY FABIO ROMEO Magnetti Marelli Design Automation Conference Las Vegas June 20th 2001 6 The Software Development Problem Product Quality is POOR Development Productivity is LOW Source Roger G Fordham Motorola Global Software Group DAC 2001 June 6 2001 Development Cycle time is TOO LONG System Software of size 10 000 Function Points QUALITY PRODUCTIVITY CYCLETIME Industry Average Industry Average Industry Average 0 44 4 13 36 Ind Best in Class Ind Best in Class Ind Best in Class 0 08 8 76 25 Customer Expectation Customer Expectation Customer Expectation 0 00044 40 3 6 Function Point per Staff Delivered Defects per Schedule in Months Month Function Point Source of Industry Data Capers Jones 2000 Software Assessments Benchmarks and Best Practices Addison Wesley 7 COMPLEXITY QUALITY TIME TO MARKET FUTURE TRENDS Time to Market Months K Lines of code SW Complexity 800 40 35 700 600 30 25 500 400 300 200 100 20 15 10 5 0 0 1995 1997 2000 2003 2005 SW defects at End of Design ppm 10000 1000 1995 1997 2000 2003 2005 KEY DRIVERS QUALITY TIME TO MARKET COMPLEXITY MGMT 100 10 1 1995 1997 2000 Telematics Body and Network 2003 2005 Power Train WINNING SOLUTIONS PLATFORM APPLICATIONS DESIGN METHODOLOGIES TESTING 8 What are the Remedies Significant commitment to CONTINUOUS IMPROVEMENT Effective use of DESIGN METHODOLOGIES Effective use of development management AUTOMATION SDL UML P PC Balance 90 10 FML 9 Software Architecture Today Poor common infrastructure Weak specialization of functions Poor resource management Poor planning 10 Software Architecture Tomorrow 11 The C or Java Paradigm Not abstract enough to capture functionality only Not detailed enough to capture important parameters such as performance energy consumption size What about real time Make it faster 12 Problems with Past Design Method Lack of unified hardware software representation Partitions are defined a priori Can t verify the entire system Hard to find incompatibilities across HW SW boundary often found only when prototype is built Lack of well defined design flow Time to market problems Specification revision becomes difficult 13 Design Effort vs System Design Value Level of Abstraction Function Design Entry Level Design Entry Level Design Entry Level ConceptualDesign Entry Level Entry Level Gap Design Design Entry Level HW SW Architecture RTL Gate platform RTL SW Today Mask ASM Tomorrow Effort Value 14 Design Effort vs System Design Value Level of Abstraction Function Design Entry Level HW SW Hand off platform Hand off platform Hand off platform Hand off platform Hand off platform Architecture RTL SW Today Mask ASM Tomorrow Effort Value 15 New Levels of Design Chain Interaction Application Space Level of Abstraction Function HW SW System Platform Architecture RTL SW Today Mask ASM Tomorrow Effort Value Architectural Space 16 High Leverage Paradigms If we face a problem that has become too complex to solve eliminate the problem Decompose Approximate Solve by construction 18 Separate Behavior from Micro architecture Implementation Architecture System Behavior Functional Specification of System Hardware and Software Optimized Computer software Rate Buffer 12 Mem 13 User Sys Control 3 External I O Sensor Synch Control 4 Front End 1 Transport Decode 2 Rate Buffer 5 Rate Buffer 9 Video Decode 6 Audio Decode Output 10 MPEG Frame Buffer 7 Video Output 8 Peripheral Audio Decode Processor Bus No notion of hardware or DSP Processor DSP RAM Control Processor System RAM Mem 11 19 Models of Computation And There are More Continuous time ODEs Spatial temporal PDEs Discrete time Rendezvous Synchronous Reactive Dataflow Each of these provides a formal framework for reasoning about certain aspects of embedded systems Tower of Babel Bruegel 1563 We are searching for an abstraction that provides the Source for all MoCs that can be obtained by refinement 20 Formalization Model of a design with precise unambiguous semantics Implicit or explicit relations inputs outputs and possibly state variables Properties Cost functions Constraints Formalization of Design Environment closed system of equations and inequalities over some algebra 21 Validating Designs By construction property is inherent By verification property is provable By simulation check behavior for all inputs By intuition property is true I just know it is By assertion property is true Wanna make something of it By
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