EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Part2 Platform based Design Application Space Application Instance Platform Mapping P Platform Design Space Export System Software Hardware Platform Platform Instance Architectural Space 1 EE249Fall06 Outline Platforms a historical perspective Platform based Design Three examples Pico radio network Unmanned Helicopter controller Engine Controller 2 EE249Fall06 Page 1 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Platform Based Design Definitions Three Perspectives S stem System Designers Semiconductor Academic ASV 3 EE249Fall06 System Definition Ericsson s E i IInternet Services S i Pl Platform f iis a new tooll ffor h helping l i CDMA operators and service providers deploy Mobile Internet applications rapidly efficiently and cost effectively Source Ericsson press release 4 EE249Fall06 Page 2 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Platform Architectures Philips Nexperia TriMedia SDRAM MMI MIPS CPU D PRxxxx I TriMedia CPU DEVICE IP BLOCK I DEVICE IP BLOCK PI BUS DVP MEMORY BUS PI BUS DEVICE IP BLOCK Middleware JavaTV TVPAK OpenTV MHP Java proprietary D TM xxxx DEVICE IP BLOCK Applications DEVICE IP BLOCK BLOCK DEVICE IP Streaming and Platform Software DVP SYSTEM SILICON Kernel pSOS VxWorks Win C K CE MIPS Nexperia Hardware Software Hardware Source Philips 5 EE249Fall06 Platform Types Communication Centric Platform SONIC Palmchip Arteris ARM Concentrates on communication Delivers communication framework plus peripherals Limits the modeling efforts SONICs Architecture DMA CPU DSP MPEG Open Core Protocol MultiChip Backplane SiliconBackplane patented C MEM I O SiliconBackplane Agent Source G Martin 6 EE249Fall06 Page 3 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Platform types Highly Programmable Platform Virtex II Pro Virtex II Pro production 3 02 Xilinx IBM PowerPC 7 00 Wind River O S 3 01 Mindspeed RocketChips SkyRail mixed signal IP gigabit serial I O acquisition 9 00 10 00 7 EE249Fall06 Quote from Tully of Dataquest 2002 This scenario places a premium on the flexibility and extensibility of the hardware platform And it discourages system architects from locking differential advantages into hardware Hence the industry will gradually swing away from its tradition of starting a new SoC design for each new application instead adapting platform chips to cover new opportunities 8 EE249Fall06 Page 4 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Outline Platforms a historical perspective Platform based Design Three examples Pico radio network Unmanned Helicopter controller Engine Controller 9 EE249Fall06 Platform Based Design concept as a major paradigm shift for Gigascale design SangiovanniVincentelli a key originator of the concept defines a platform as EETimes 20th Year Anniversary Edition September 12 2002 10 Source Jan Rabaey EE249Fall06 Page 5 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Platform based Design ASV Triangles 1998 Tensilica Xtensa RISC CPU ASICs Application Space SRAM Application Instance Sonics Silicon Backplane Platform Mapping Speech Samples Interface UART Interface External Bus Interface System Software Hardware Platform Platform Design Space Export Flash Wireless Processor Protocol Baseband Processor Bus Platform Instance Architectural Space p Xilinx FPGA ADC DAC RF Frontend Intercom Platform BWRC 2001 Platform library of resources defining an abstraction layer hide unnecessary details 11 expose only relevant parameters for the next step EE249Fall06 Principles of Platform methodology Meet in the Middle Top Down Define a set of abstraction layers From specifications at a given level select a solution controls components in terms of components Platforms of the following layer and propagate constraints Bottom Up Platform components e g micro controller RTOS communication primitives at a given level are abstracted to a higher level by their functionality and a set of parameters that help guiding the solution selection process The selection process is equivalent to a covering problem if a common semantic domain is used 12 EE249Fall06 Page 6 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Separation of Concerns 1990 Vintage Behavior Components IPs Matlab Virtual Architectural Components C Code ASCET Buses CPUs Buses Buses Operating Systems Analysis Develop pment Process System Behavior Specification f1 System Platform f2 ECU 1 ECU f3 Bus Evaluation of Architectural and Partitioning Alternatives Mapping Implementation Performance Analysis Calibration ECU 2 ECU ECU 3 ECU Refinement After Sales Service EE249Fall06 Platform based Design Application Space Architectural Space Platform Instance Application Instance Platform Pl tf Mapping Platform Design Space Export Platform library of resources defining an abstraction layer hide unnecessary details expose only relevant parameters for the next step 14 EE249Fall06 Page 7 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test The Fractal Nature of Design Architecture Platform Platform m Function Semantic Platform Architecture Platform Platform Function Semantic Platform 15 EE249Fall06 Analog Platforms Platform characterization Analog Constraint Graphs conservative configuration space Adaptive characterization process Developed tools for platform characterization client server framework with GUI system exploration AP specific Simulated Annealing Optimizer Case studies UMTS receiver 2 LNA platforms 1 mixer Interface modeling LNA mixer Behavioral models validation System exploration ADC residue amplifier OpAmp platform Digital calibration for linearity Exploration of power linearity tradeoffs with calibration Next steps Automatic generation of conservative ACG schedules New case studies with the BWRC Picoradio base band power estimation Extension to higher level platforms 16 EE249Fall06 Page 8 EE249 Fall 2007 The MARCO DARPA Gigascale Silystem Research Center for Design Test Platform Based Implementation Platforms eliminate large loop iterations for affordable design Restrict design space via new forms of regularity and structure that surrender some design potential for lower cost and first pass success The Th number b and d llocation ti off iintermediate t di t platforms l tf iis th the
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