Verilog Code Generation for an ASIP Design Environment Nathan Kitchen Vinay Krishnan Mentor Scott Weber MESCAL EE 244 249 Joint Project Fall 2002 Outline Motivation Design Environment Approach Example Motivation Three ways to design a programmable system ASIP Specify its micro architecture and the intractable in general operations it performs the instruction set and verify that they are consistent Synthesize a micro architecture from the ISA Specify the micro architecture and extract the operations it supports need architectural hints and behavioral synthesis We are here Bottom up Instruction Set Design Traditional Top down Design Bottom up Design instruction set space ISA is fixed Any of these instruction sets can implement the application architecture exploration micro architecture space micro architecture space Teepee Design environment for MESCAL Multi view methodology Common data model for generating simulator assembler compiler and netlist Views are abstractions of the model Can only use information present in the model Not allowed to introduce new semantics Architecture view designer lays out datapath Operation view extracts operations from architecture Simulator view generates simulator program Hardware view generates synthesizable Verilog our project Advantage of Multi View Design C RTL simulation gates silicon synthesis Traditional hard to verify equivalence of simulator and RTL written separately data model C RTL simulation gates silicon easier to verify synthesis correctness of transformations from common data model Architecture View Actors connected by signals between ports Semantics of atomic actors defined by firing rules sel in out or fire in 0 p 1 int32 in 1 p 0 sel p 1 e out p 1 int32 out in 0 fire in 1 p 1 int32 in 0 p 0 sel p 1 e out p 1 int32 out in 1 no fire in 0 p 0 in 1 p 0 sel p 0 e out p 0 Port Color Meaning p 0 Signal is not present its data is invalid p 1 Signal is present p 1 e Signal is present and is an enumeration Composite actors hierarchy p 1 int allow Signal is present and is a bit vector Composing Actors in sel in out in inc out dec out sel in out Control ports select lines are left unconnected Their values will be determined in the operation view Operation View Solve constraints on firing rules Iterative SAT procedure Only minimal solutions Operation 1 Operation 2 Operation 3 Instruction Models Composite1 Composite2 i 1 i 2 Composite1 has separate instruction models for NOP i 1 and i 2 Composite2 has one instruction model for both i 1 and i 2 Approach cut to Vinay A Sample Architecture View Fetch Unit Program Counter Verilog Structure Preserve the hierarchical structure of the Architecture View Atomic actors Atomic modules Composite actors Composite modules Atomic Modules Actor semantics implemented with behavioral Verilog Two parts combinational logic and sequential state write Procedural always blocks implemented for both Combinational logic in always blocks instead of assigns to avoid potential mux chains Composite Modules Act as containers for the modules inside them Instantiate the inner modules Route the wires appropriately Merge control signals based on instruction models Ground unconnected ports if any Top Level Module Decodes instruction word opcode parameter1 parameter2 Converts opcodes to control signals which activate concerned atomic actors one hot encoding of opcodes control signals Multiple issue width achieved by multiple hot encoding Results Tools ModelSimPE 5 5ed Synplicity Pro 7 1 Circuit Schematic architecture view Fetch Unit architecture view Program Counter architecture view Questions The Answer 42 Prior Work Architecture description languages Behavioral ADLs Describe instruction semantics Lack information for synthesizing micro architecture Mixed ADLs Describe semantics and micro architecture Tightly coupled with specific tools Hardware description languages e g Verilog Can describe any micro architecture No concept of operations Future Work Combine operations into more conventional instructions in assembler or compiler view Multiple PEs
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