DOC PREVIEW
Berkeley ELENG C249A - Verilog Code Generation for an ASIP Design Environment

This preview shows page 1-2-3-25-26-27 out of 27 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 27 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Verilog Code Generation for an ASIP Design EnvironmentOutlineMotivationBottom-up Instruction Set DesignTeepeeAdvantage of Multi-View DesignArchitecture ViewComposing ActorsOperation ViewInstruction ModelsApproachA Sample Architecture ViewFetch UnitProgram CounterVerilog StructureAtomic ModulesComposite ModulesTop-Level ModuleResults!ToolsCircuit SchematicSlide 22Slide 23Questions?The Answer:Prior WorkFuture WorkVerilog Code Generation for an ASIP Design EnvironmentNathan KitchenVinay KrishnanMentor: Scott Weber (MESCAL)EE 244/249 Joint ProjectFall 2002Outline•Motivation•Design Environment•Approach•ExampleMotivation•Three ways to design a programmable system (ASIP):Specify its micro-architecture and the operations it performs (the instruction set) and verify that they are consistentintractable in generalSynthesize a micro-architecture from the ISA need architectural hints and behavioral synthesisSpecify the micro-architecture and extract the operations it supportsWe are hereBottom-up Instruction Set DesignTraditional Top-down DesignISA is fixedmicro-architecture spaceinstruction set spacemicro-architecture spaceAny of these instruction sets can implement the application.Bottom-up Designarchitecture explorationTeepee•Design environment for MESCAL•Multi-view methodology–Common data model for generating simulator, assembler, compiler, and netlist –Views are abstractions of the model•Can only use information present in the model•Not allowed to introduce new semantics–Architecture view: designer lays out datapath–Operation view: extracts operations from architecture–Simulator view: generates simulator program–Hardware view: generates synthesizable Verilog (our project)Advantage of Multi-View DesignsynthesissimulationRTLgatessiliconC≡?simulationsynthesisdata modelRTLgatessiliconCTraditional: hard to verify equivalence of simulator and RTL written separatelyeasier to verify correctness of transformations from common data modelArchitecture View•Actors connected by signals between ports•Semantics of atomic actors defined by firing rules•Composite actors allow hierarchyor(fire(in[0].p.1.int32, in[1].p.0, sel.p.1.e, out.p.1.int32) {out = in[0];} fire(in[1].p.1.int32, in[0].p.0, sel.p.1.e, out.p.1.int32) {out = in[1];} no_fire(in[0].p.0, in[1].p.0, sel.p.0.e, out.p.0) {} )outinselPort Color Meaning.p.0 Signal is not present (its data is invalid)..p.1 Signal is present..p.1.e Signal is present and is an enumeration..p.1.int Signal is present and is a bit vector.Composing ActorsControl ports (select lines) are left unconnected. Their values will be determined in the operation view.outinselincincinoutdecdecinoutoutinselOperation ViewSolve constraints on firing rules•Iterative SAT procedure•Only minimal solutionsOperation 1Operation 2Operation 3Instruction Models•Composite1 has separate instruction models for NOP, i_1, and i_2•Composite2 has one instruction model for both i_1 and i_2Composite1Composite2i_2i_1Approach(cut to Vinay)A Sample Architecture View>>Fetch Unit>>Program Counter>>Verilog Structure•Preserve the hierarchical structure of the Architecture View•Atomic actors => Atomic modules•Composite actors => Composite modulesAtomic Modules•Actor semantics implemented with behavioral Verilog•Two parts: combinational logic and sequential state write•Procedural ‘always’ blocks implemented for both•Combinational logic in ‘always’ blocks instead of ‘assigns’ to avoid potential mux chainsComposite Modules•Act as containers for the modules inside them•Instantiate the inner modules•Route the wires appropriately•Merge control signals based on instruction models•Ground unconnected ports, if anyTop-Level Module•Decodes instruction word•Converts opcodes to control signals which activate concerned atomic actors (one hot encoding of opcodes->control signals)•Multiple issue width achieved by multiple-hot encoding!opcodeparameter1parameter2Results!Tools•ModelSimPE 5.5ed•Synplicity Pro 7.1Circuit Schematicarchitecture viewFetch Unitarchitecture viewProgram Counterarchitecture viewQuestions?The Answer:42Prior Work•Architecture description languages–Behavioral ADLs•Describe instruction semantics•Lack information for synthesizing micro-architecture–Mixed ADLs•Describe semantics and micro-architecture•Tightly coupled with specific tools•Hardware description languages (e.g., Verilog)–Can describe any micro-architecture–No concept of operationsFuture Work•Combine operations into more conventional instructions in assembler or compiler view•Multiple


View Full Document

Berkeley ELENG C249A - Verilog Code Generation for an ASIP Design Environment

Documents in this Course
Load more
Download Verilog Code Generation for an ASIP Design Environment
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Verilog Code Generation for an ASIP Design Environment and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Verilog Code Generation for an ASIP Design Environment 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?