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Berkeley ELENG C249A - What Is a Compiler When The Architecture Is Not Hard(ware) ?

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What Is a Compiler When The Architecture Is Not Hard(ware) ?Embedded ComputingThe Nature of Embedded SystemsFavorable TrendsEmbedded Systems DesiderataTiming ExampleCurrent ArtSubtle but Sure HurdlesThe Embedded Systems ChallengeResponding Via AutomationThree Active ApproachesCustom Processor ImplementationArchitecture Exploration and SynthesisCustom MicroprocessorsApplication Specific DesignThe Compiler Optimization TrajectoryWhat Is the Compiler’s Target ``ISA’’?Choices of SiliconReconfigurable ComputingFPGAs As an Alternative Choice for CustomizationMajor MotivationsAdaptive EPICPowerPoint PresentationSlide 24Slide 25Slide 26Slide 27Slide 28Slide 29AEPIC CompilationKey Tasks For AEPIC CompilerSlide 32Slide 33Managing Reconfigurable Resource (contd.)The Problem With Long Reconfiguration TimesSpeculating Configuration LoadsSample Compiler TopicsMore Generally Architecture AssemblyUCB November 8, 2001 Krishna V Palem Georgia Tech What Is a Compiler When The What Is a Compiler When The Architecture Is Not Hard(ware) ?Architecture Is Not Hard(ware) ?Krishna V PalemThis work was supported in part by awards from Hewlett-Packard Corporation, IBM, Panasonic AVC, and by DARPA under Contract No. DABT63-96-C-0049 and Grant No. 25-74100-F0944.Portions of this presentation were given by the speaker as a keynote at the ACM LCTES2001 and as an invited speaker at EMSOFT012UCB – November 8, 2001 Krishna V Palem Georgia Tech Embedded ComputingWhy ?What ?How ?3UCB – November 8, 2001 Krishna V Palem Georgia Tech The Nature of Embedded SystemsVisible ComputingView is of end application(Hidden computing element)4UCB – November 8, 2001 Krishna V Palem Georgia Tech -Supported by Moore’s (second) law–Computing power doubles every eighteen monthsCorollary: cost per unit of computing halves every eighteen months-From hundreds of millions to billions of units-Projected by market research firms (VDC) to be a 50 billion+ space over the next five years-High volume, relatively low per unit $ marginFavorable Trends5UCB – November 8, 2001 Krishna V Palem Georgia Tech Embedded Systems Desiderata-Low Power- High battery life-Small size or footprint-Real-time constraintsPerformance comparable to or surpassing leading edge COTS technologyRapid time-to-market6UCB – November 8, 2001 Krishna V Palem Georgia Tech Timing ExamplePredictable Timing BehaviorUnpredictable TimingBehaviorVideo-On-Demand7UCB – November 8, 2001 Krishna V Palem Georgia Tech Current Art-Meet desiderata while overcoming NRE cost hurdles through volume-High migration inertia across applications-Long time to marketVertical application domainsIndustrial AutomationTelecomSelect computational kernelsTo ASIC8UCB – November 8, 2001 Krishna V Palem Georgia Tech Subtle but Sure Hurdles-For Moore’s corollary to be true–Non-recurring engineering (NRE) cost must be amortized over high-volume–Else prohibitively high per unit costs-Implies “uniform designs” over large workload classes–(Eg). Numerical, integer, signal processing-Demands of embedded systems–“Non uniform” or application specific designs–Per application volume might not be high–High NRE costs  infeasible cost/unit–Time to market pressure9UCB – November 8, 2001 Krishna V Palem Georgia Tech The Embedded Systems Challenge-Sustain Moore’s corollary–Keep NRE costs downMultiple application domains3D GraphicsIndustrial AutomationMedtronics E-Textiles Telecom Rapidly changing application kernels in moderate volumeCustom computing solution meeting constraints10UCB – November 8, 2001 Krishna V Palem Georgia Tech Responding Via AutomationMultiple application domains3D GraphicsIndustrial AutomationMedtronics E-Textiles Telecom Rapidly changing application kernels in low volumeAutomaticToolsPower TimingSizeApplication specific design11UCB – November 8, 2001 Krishna V Palem Georgia Tech Three Active Approaches-Custom microprocessors-Architecture exploration and synthesis-Architecture assembly for reconfigurable computing12UCB – November 8, 2001 Krishna V Palem Georgia Tech Custom Processor Implementation-High performance implementation-Customized in silicon for particular application domain-O(months) of design time-Once designed, programmable like standard processorsProprietaryToolsProprietary ISA, Architecture Specification Application analysisFabricate ProcessorCustom Processor implementationApplication Language with custom extensionsCompiler BinaryProprietary ISATime IntensiveTensilica, HP-ST Microelectronics approach13UCB – November 8, 2001 Krishna V Palem Georgia Tech Architecture Exploration and Synthesis The PICO VisionProgram InAutomatic synthesis of application specific parallel / VLIWULSI microprocessorsAnd their compilersfor embedded computingChip Out“Computer design for the masses” “A custom system architecture in 1 week tape-out in 4 weeks”B Ramakrishna Rau “The Era of Embedded Computing”, Invited talk, CASES 2000.14UCB – November 8, 2001 Krishna V Palem Georgia Tech Custom MicroprocessorsApplication(s)define workloadOptimizingCompilerAnalyzeDefine ISA extension (eg) IA 64+Define CompilerOptimizationsDesign ImplementationMicroprocessor(eg) Itanium +15UCB – November 8, 2001 Krishna V Palem Georgia Tech Application Specific DesignSingleApplicationProgram AnalysisAnalyzeLibrary of possible implementations(Bypass ISA)Explore andSynthesize implementationsVLIW Core + Non programmable extensionApplicationsApplication specific processor runs single applicationExtended EPIC Compiler Technology16UCB – November 8, 2001 Krishna V Palem Georgia Tech The Compiler Optimization TrajectoryFrontend and OptimizerDetermine DependencesDetermine IndependencesBind Operations to Function UnitsBind Transports to BussesDetermine DependencesBind Transports to BussesExecuteSuperscalarDataflowIndep. Arch.VLIWTTACompiler HardwareDetermine IndependencesBind Operations to Function UnitsB. Ramakrishna Rau and Joseph A. Fisher. Instruction-level parallel: History overview, and perspective. The Journal of


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