What Is a Compiler When The Architecture Is Not Hard ware Krishna V Palem This work was supported in part by awards from Hewlett Packard Corporation IBM Panasonic AVC and by DARPA under Contract No DABT63 96 C 0049 and Grant No 25 74100 F0944 Portions of this presentation were given by the speaker as a keynote at the ACM LCTES2001 and as an invited speaker at EMSOFT01 UCB November 8 2001 Krishna V Palem Georgia Tech 2 Embedded Computing Why What How UCB November 8 2001 Krishna V Palem Georgia Tech The Nature of Embedded Systems Visible Computing View is of end application Hidden computing element UCB November 8 2001 Krishna V Palem Georgia Tech 3 4 Favorable Trends Supported by Moore s second law Computing power doubles every eighteen months Corollary cost per unit of computing halves every eighteen months From hundreds of millions to billions of units Projected by market research firms VDC to be a 50 billion space over the next five years High volume relatively low per unit margin UCB November 8 2001 Krishna V Palem Georgia Tech 5 Embedded Systems Desiderata Low Power High battery life Small size or footprint Real time constraints Performance comparable to or surpassing leading edge COTS technology UCB November 8 2001 Rapid time to market Krishna V Palem Georgia Tech 6 Timing Example Video On Demand Predictable Timing Behavior UCB November 8 2001 Unpredictable Timing Behavior Krishna V Palem Georgia Tech 7 Current Art Vertical application domains Telecom Industrial Automation Select computational kernels To ASIC Meet desiderata while overcoming NRE cost hurdles through volume High migration inertia across applications Long time to market UCB November 8 2001 Krishna V Palem Georgia Tech 8 Subtle but Sure Hurdles For Moore s corollary to be true Non recurring engineering NRE cost must be amortized over high volume Else prohibitively high per unit costs Implies uniform designs over large workload classes Eg Numerical integer signal processing Demands of embedded systems Non uniform or application specific designs Per application volume might not be high High NRE costs infeasible cost unit Time to market pressure UCB November 8 2001 Krishna V Palem Georgia Tech The Embedded Systems Challenge Multiple application domains 3D Industrial Graphics Automation Medtronics E Textiles Telecom Rapidly changing application kernels in moderate volume Custom computing solution meeting constraints Sustain Moore s corollary Keep NRE costs down UCB November 8 2001 Krishna V Palem Georgia Tech 9 10 Responding Via Automation Multiple application domains 3D Industrial Graphics Automation Medtronics E Textiles Telecom Rapidly changing application kernels in low volume Power Size UCB November 8 2001 Automatic Tools Application specific design Timing Krishna V Palem Georgia Tech 11 Three Active Approaches Custom microprocessors Architecture exploration and synthesis Architecture assembly for reconfigurable computing UCB November 8 2001 Krishna V Palem Georgia Tech Custom Processor Implementation Application analysis Application Proprietary ISA Fabricate Architecture Processor Specification Proprietary Tools Language with custom extensions Compiler Binary Custom Processor implementation Proprietary ISA Time Intensive High performance implementation Customized in silicon for particular application domain O months of design time Once designed programmable like standard processors Tensilica HP ST Microelectronics approach UCB November 8 2001 12 Krishna V Palem Georgia Tech Architecture Exploration and Synthesis The PICO Vision Program In Automatic synthesis of application specific parallel VLIW ULSI microprocessors And their compilers for embedded computing Computer design for the masses Chip Out A custom system architecture in 1 week tape out in 4 weeks B Ramakrishna Rau The Era of Embedded Computing Invited talk CASES 2000 UCB November 8 2001 Krishna V Palem Georgia Tech 13 14 Custom Microprocessors Application s define workload Optimizing Compiler Microprocessor eg Itanium UCB November 8 2001 Analyze Define Compiler Optimizations Define ISA extension eg IA 64 Design Implementation Krishna V Palem Georgia Tech 15 Application Specific Design Applications Single Application Analyze Program Analysis Extended EPIC Compiler Technology Explore and Synthesize implementations Library of possible implementations Bypass ISA VLIW Core Non programmable extension Application specific processor runs single application UCB November 8 2001 Krishna V Palem Georgia Tech The Compiler Optimization Trajectory Compiler Hardware Frontend and Optimizer Superscalar Determine Dependences Dataflow Determine Dependences Determine Independences Indep Arch Determine Independences Bind Operations to Function Units VLIW Bind Operations to Function Units Bind Transports to Busses Bind Transports to Busses TTA Execute B Ramakrishna Rau and Joseph A Fisher Instruction level parallel History overview and perspective The Journal of Supercomputing 7 1 2 9 50 May 1993 UCB November 8 2001 Krishna V Palem Georgia Tech 16 What Is the Compiler s Target ISA Compiler Frontend and Optimizer Determine Dependences Determine Independences Hardware Superscalar Dataflow Indep Arch Bind Operations to Function Units VLIW Bind Transports to Busses Determine Dependences Determine Independences Bind Operations to Function Units Bind Transports to Busses TTA Execute B Ramakrishna Rau and Joseph A Fisher Instruction level parallel History overview and perspective The Journal of Supercomputing 7 1 2 9 50 May 1993 UCB November 8 2001 Target is a range of architectures and their building blocks Compiler reaches into a constrained space of silicon Explores architectural implementations O days weeks of design time Exploration sensitive to application specific hardware modules Fixed function silicon is the result Verification NRE costs still there One approach to overcoming time to market Krishna V Palem Georgia Tech 17 18 Choices of Silicon High level design synthesis EDIF Netlist Fixed silicon implementation Standard cell design etc UCB November 8 2001 Emulated i e Reconfigurable target Krishna V Palem Georgia Tech 19 Reconfigurable Computing UCB November 8 2001 Krishna V Palem Georgia Tech FPGAs As an Alternative Choice for Customization Frequent re configuration and hence frequent recustomization Fabrication process is steadily improving Gate densities are going up Performance levels are acceptable Amortize large NRE investments by using COTS platform UCB November
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