Challenges Shift to u Reuse Strategy u Higher Level of Abstractions u Software 1 PERCENT OF TRANSISTORS WITHIN EMBEDDED IP EXCLUDES MEMORY 100 Transistors Random Logic Transistors Transistors Within Embedded IP 5 Year 1997 1998 1999 2000 2001 2002 2003 2004 2005 Feature Dimension m 0 35 0 25 0 18 0 15 0 13 0 11 0 10 0 08 0 07 2 TRENDS IN EMBEDDED IP 1998 1999 2000 2001 2002 2003 2004 2005 2006 112 005 133 426 174 723 164 592 173 506 197 118 227 752 269 078 313 214 NA 19 1 31 0 5 4 13 6 15 5 18 1 16 4 43 506 50 493 64 366 67 581 76 034 92 804 115 123 145 700 175 767 Growth rate NA 16 1 27 5 5 0 12 5 22 1 24 0 26 6 20 6 Percent total 38 8 37 8 36 8 41 1 43 8 47 1 50 5 54 1 56 1 IP based design Value M 15 706 19 894 30 123 39 129 51 247 68 582 90 602 122 679 153 093 NA 26 7 51 4 29 9 31 0 33 8 32 1 35 4 24 8 36 1 39 4 46 8 57 9 67 4 73 9 78 7 84 2 87 1 Total IC Value M Growth rate System IC Value M Growth rate 400 Percent system IC 5 8 350 DESIGNS WITH EMBEDDED IP WILL DOMINATE THE SYSTEM IC BUSINESS IN THE FUTURE Value B 300 250 IC Market 200 150 100 Designs With Embedded IP 50 System IC Market 0 1998 1999 2000 2001 2002 2003 2004 2005 2006 Year 3 Image borrowed from an Iomega advertisement for Y2K software and disk drives Scientific American September 1999 Computing for Embedded Systems 4 EMBEDDED SYSTEM THE REAL STORY FABIO ROMEO Design Automation Conference Las Vegas June 20th 2001 5 COMPLEXITY QUALITY TIME TO MARKET TODAY PWT UNIT BODY GATEWAY INSTRUMENT CLUSTER TELEMATIC UNIT MEMORY 256 KB 128 KB 184 KB 8 MB LINES OF CODE 50 000 30 000 45 000 300 000 PRODUCTIVITY 6 LINES DAY 10 LINES DAY 6 LINES DAY 10 LINES DAY 3000 PPM 2500 PPM 2000PPM 1000 PPM 3 YEARS 2 YEARS 1 YEAR 1 YEAR DEV EFFORT 40 MANMAN YEAR 12 MANMAN YEAR 30 MANMAN YEAR 200 MANMAN YEAR VALIDATION TIME 5 MONTHS 1 MONTH 2 MONTHS 2 MONTHS TIME TO MARKET 24 MONTHS 18 MONTHS 12 MONTHS 12 MONTHS RESIDUAL DEFECT RATE END OF DEV CHANGING RATE C CODE 6 COMPLEXITY QUALITY TIME TO MARKET FUTURE TRENDS Time to Market Months K Lines of code SW Complexity 800 700 600 500 400 300 200 100 0 40 35 30 25 20 15 10 5 0 1995 1997 2000 2003 2005 SW defects at End of Design ppm 10000 1000 1995 1997 2000 2003 2005 KEY DRIVERS QUALITY TIME TIME TO TO MARKET COMPLEXITY MGMT 100 10 1 1995 1997 2000 Telematics 2003 2005 Power Train WINNING SOLUTIONS PLATFORM APPLICATIONS DESIGN METHODOLOGIES TESTING Body and Network 7 Software Productivity Roger G Fordham Director Performance Excellence Motorola Global Software Group Roger Fordham Motorola com June 6 2001 The Software Development Problem u Product Quality is POOR u Development Productivity is LOW u Development Cycle time is TOO LONG System Software of size 10 000 Function Points QUALITY PRODUCTIVITY CYCLETIME Industry Average Industry Average Industry Average 0 44 4 13 36 Ind Best in Class Ind Best in Class Ind Best in Class 0 08 8 76 25 Customer Expectation Customer Expectation Customer Expectation 0 00044 40 3 6 Delivered Defects per Function Point Function Point per Staff Month Schedule in Months Source of Industry Data Capers Jones 2000 Software Assessments Benchmarks and Best Practices Addison Wesley pp339 340 9 What are the Remedies u Significant commitment to CONTINUOUS IMPROVEMENT u Effective use of DESIGN METHODOLOGIES u Effective use of development management AUTOMATION SDL UML P PC Balance FML 90 10 10 Software Architecture Today Poor common infrastructure Weak specialization of functions Poor resource management Poor planning 11 Software Architecture Tomorrow 12 The C or Java Paradigm uNot abstract enough to capture functionality only uNot detailed enough to capture important parameters such as performance energy consumption size 13 What about real time Make it faster 14 Problems with Past Design Method uLack of unified hardware software representation uPartitions are defined a priori s Can t verify the entire system s Hard to find incompatibilities across HW SW boundary often found only when prototype is built uLack of well defined design flow s Time to market problems s Specification revision becomes difficult 15 Design Effort vs System Design Value Level of Abstraction Function Design Entry Level Design Entry Level Design Entry Level ConceptualDesign Entry Level Entry Level Gap Design Design Entry Level HW SW Architecture RTL Gate platform RTL SW Today Mask ASM Tomorrow Effort Value 16 Design Effort vs System Design Value Level of Abstraction Function Design Entry Level HW SW Hand off platform Hand off platform Hand off platform Hand off platform Hand off platform Architecture RTL SW Today Mask ASM Tomorrow Effort Value 17 New Levels of Design Chain Interaction Application Space Level of Abstraction Function HW SW System Platform Architecture RTL SW Today Mask ASM Tomorrow Effort Value Architectural Space 18 High Leverage Paradigms If we face a problem that has become too complex to solve eliminate the problem s Decompose s Approximate s Solve by construction 20 Separate Behavior from Micro architecture uImplementation Architecture s s Functional Specification of System No notion of hardware or software Mem 13 Rate Buffer 12 User Sys Control 3 Sensor Synch Control 4 Front End 1 Transport Decode 2 Rate Buffer 5 Rate Buffer 9 Video Decode 6 Audio Decode Output 10 s Hardware and Software s Optimized Computer MPEG Frame Buffer 7 Video Output 8 DSP Processor External I O Peripheral Audio Decode Processor Bus uSystem Behavior DSP RAM Control Processor System RAM Mem 11 21 Models of Computation And There are More u Continuous time ODEs u Spatial temporal PDEs u Discrete time u Rendezvous u Synchronous Reactive u Dataflow u Each of these provides a formal framework for reasoning about certain aspects of embedded systems Tower of Babel Bruegel 1563 We are searching for an abstraction that provides the Source for all MoCs that can be obtained by refinement 22 Formalization Model of a design with precise unambiguous semantics u Implicit or explicit relations inputs outputs and possibly state variables u Properties u Cost functions u Constraints Formalization of Design Environment closed system of equations and inequalities over some algebra 23 Validating Designs u By construction s property is inherent u By verification s property is provable u By simulation s check behavior for all inputs u By intuition s property is true I just know it is u By assertion s property is true Wanna make something of it u By intimidation s Don t even try to doubt whether it is true It is generally better to
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