System-Level Tools to Accelerate FPGA Design for Signal ProcessingWhy FPGA DSP?Exploiting Parallelism: Conventional DSP SolutionsDSP Systems in FPGAsFPGA as DSP PlatformWhat Language?{System}C{++}?{System}C{++}?++A Fallacy1A Picture is Worth…SimulinkSystem Generator for DSPAdvanced Hardware Lab Circa 1984Advanced Hardware Lab 2002System Generator for DSPSystem Generator (cont.)SysGen Modeling: AnalysisSysGen ModelingA Simple MAC EngineCORDIC ProcessorCORDIC Processor (cont.)LMS Adaptive FilterPipelined LMS AlgorithmLMS Adaptive UpdateQAM ReceiverSystem Generator ModelEmbedded DSPEmbedded DSP (cont.)Using SysGen to Create CoreConnectTM PeripheralsSysGen Peripheral OverviewModeling Bus TransactionsThe FutureSystem-Level Toolsto Accelerate FPGADesign for SignalProcessingJim HwangSr. Manager, DSP Software andDesign MethodologiesWhy FPGA DSP?• High performance• Flexibility• Time to Market• Functional extensions to existing equipment• Standard part (no NRE/Inventory issues)• Early system bring-up on hardwareUp to 12.5 milliongatesEmbeddedRISC CPUSynchronous Dual-Port RAMBRAMProgrammableFabric (300+ MHz)SwitchMatrixSwitchMatrixCLB,IOB,DCMCLB,IOB,DCM3.125Gb SerialProgrammableI/Os with LVDS50 ΩImpedanceControllerXCITEImpedanceControl• 18b x 18b multiplier• 300MHz pipelinedMultipliersThe Highly Parallel Signal ProcessorExploiting Parallelism:Conventional DSP Solutions• New DSP architectures such as VLIW and super-scalarhave one goal: provide higher degrees of parallelism• Architecture evolution along this design axis does not scale– Too many MAC functional units makes programming, compilersand scheduling difficult• The effective computing per chip area decreases– Memories grow geometrically while the datapath does notDSP Systems in FPGAs• Device technology is only part of the solution• The software and IP are complex, and historically have beena barrier to entry• Require design methodologies for– Productivity– Rapid design exploration– Hardware abstraction• Single source for the entire design & development cycle– Modeling– Verification– Implementation– Automatic code generationFPGA as DSP Platform• Like other ASICs, the FPGA is largely a value propositionfor very high performance applications– Digital communications infrastructure– Software defined radio– Video & imaging– SAR, adaptive arrays & beamforming• This has profound implications for design methodology– DSP & microprocessors are very good at tasks whereperformance is not a problem– Not targeting (most of) the tera-bytes of legacy DSP code (yet)– Spartan-II family devices counter this trendWhat Language?• Do you use MATLAB?• Why do we like it?• Easy to learn• Interpreted• High level abstractions• Extensive libraries and built-in functions• Rich facilities for data analysis and visualization• Used in many signal processing textbooks• But is it a good language for specifying hardware?• Imperative language with sequential semantics• No concurrency model• Dynamically typed (flexible, but…){System}C{++}?• Considerable activity advocating imperative, sequentiallanguages for system level design– C, C++, SystemC– Co-Ware, Synopsys, Cadence• This is not a bad thing for– Embedded systems– High-level (e.g. untimed, untyped) functional modeling– Validation of complex systems• This is not a good thing for– Hardware description– High-performance DSP system design{System}C{++}?++• Language designers give a lot of thought to semantics– C/C++ semantics derived from microprocessor considerations– A good language for hardware must model concurrency– Object oriented principles are not a cure for semantic flaws• Hardware synthesis (from C) is not a solved problem– High-performance circuits carefully tuned to target technology– All “C”-based design flows depend on design iteration to the pointof “RTL” code before synthesis– At this level of abstraction, C/C++ becomes contorted– VHDL may not be beautiful, but it models concurrency wellA Fallacy11Observed by Bob Broderson (UCB)• Premise: “software” is easier than “hardware”, consequently,systems should be specified in the language of software engineers• Empirical evidence to contrary• Software products invariably ship with more bugs thanhardware products• There are more software engineers at Xilinx than hardwareengineers• Conclusion: do not assume that (imperative, sequential) “software”languages are best suited for DSP hardware and systemspecificationA Picture is Worth…• Visual languages and development environments– Synchronous Data Flow– Ptolemy (UCB)– SPW (Cadence)– Simulink (MathWorks)• Classical DSP algorithm description• Block diagrams• Signal flow graphs• Inherently concurrent• A good match!Simulink• Graphical simulation environment– Continuous and discrete time dynamical systems– Well suited for modeling hardware (and getting better)• Block libraries for DSP, communications, imageprocessing, digital control, and much more• Open architecture– Extensible– Public APIs– Amenable to programming in C, C++, Java, …• MATLAB inside (and underneath)– The implications should not be underestimatedSystem Generator for DSP• Xilinx software for FPGA modeling & implementation• FPGA interfaces provided in Simulink environment– Libraries of functions for modeling DSP (and other) systems– Automatic code generation of FPGA circuits– Fast on-ramp into the FPGA• System level abstractions create new opportunities in the lab– Explore architectures for DSP algorithms– Implementation issues (e.g. quantization, pipelining)– Emphasize system level test and test bench methodologies– Actually run the system in silicon!Advanced Hardware LabCirca 1984Got wirewrap?Advanced Hardware Lab2002Got System Generator?xc2v2000e FPGASystem Generator for DSP• Visual data flow paradigm• Polymorphic block libraries• Bit and cycle true modeling• Seamlessly integrated withSimulink and MATLAB– Test bench and data analysis• Automatic code generation– Synthesizable VHDL– IP cores– HDL test bench– Project and constraint filesSystem Generator (cont.)• Supports common Simulink idioms– Data type propagation– Polymorphic blocks– Sample time propagation– Block customization– MATLAB hooksSysGen Modeling: Analysis• Observing quantization effectsQuantization Error Block– All fixed point data
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