CPU Modeling and Use for Embedded SystemsOutlineWhat is “Computer Architecture”?The Instruction Set: a Critical InterfaceLevels of Representation (61C Review)Execution CycleFast, Pipelined Instruction Interpretation5 Steps of MIPS DatapathFigure 3.4, Page 134 , CA:AQA 2eRelationship of Caching and PipeliningA Modern Memory HierarchyThe Other 90% of ArchitectureOutlineSimpleScalar OverviewSimpleScalar ToolsuiteSimpleScalar ConclusionsLiberty Simulation EnvironmentLiberty ConclusionsModeling Microprocessors in MetropolisModeling with YAPI + KPNSingle Process YAPI Model*Out-of-Order ArchitecturesARM Modeling OverviewDouble Process ModelDouble Process ModelModels with MemoryICache UsageDCache UsageAn Abstract Speculative ModelISA_ML OverviewSample Instructions: Base InstructionSample Instructions: Other InstructionsModeling Microprocessors in Metropolis: ConclusionsOutlineAccuracy vs Performance vs CostTraditional CosimulationCo-Simulation in MetropolisBackwards AnnotationBack Annotation: Overall PictureBack Annotation: ExampleFinal WordsCPU Modeling and Use for CPU Modeling and Use for Embedded SystemsEmbedded SystemsLecturer: Trevor MeyerowitzLecturer: Trevor MeyerowitzEE249 Embedded Systems DesignEE249 Embedded Systems DesignProfessor: Professor: Alberto SangiovanniAlberto Sangiovanni--VincentelliVincentelliOctober 21October 21stst, 2004, 2004etropolis2OutlineOutlineIntroductionIntroductionMotivationMotivationComputer Architecture in 10 Minutes FlatComputer Architecture in 10 Minutes FlatProcessor ModelingProcessor ModelingUse of Processor Modeling in Embedded SystemsUse of Processor Modeling in Embedded SystemsConclusionsConclusionsCS252/CullerLec 1.31/22/02What is “Computer Architecture”?I/O systemInstr. Set Proc.CompilerOperatingSystemApplicationDigital DesignCircuit DesignInstruction SetArchitectureFirmware• Coordination of many levels of abstraction• Under a rapidly changing set of forces• Design, Measurement, andEvaluationDatapath & Control LayoutCS252/CullerLec 1.41/22/02The Instruction Set: a Critical Interfaceinstruction setsoftwarehardwareCS252/CullerLec 1.51/22/02Levels of Representation (61C Review)High Level Language ProgramAssembly Language ProgramMachine Language ProgramControl Signal SpecificationCompilerAssemblerMachine Interpretationtemp = v[k];v[k] = v[k+1];v[k+1] = temp;lw $15,0($2)lw $16,4($2)sw $16, 0($2)sw $15, 4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 °°ALUOP[0:3] <= InstReg[9:11] & MASKCS252/CullerLec 1.61/22/02Execution CycleInstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstructionObtain instruction from program storageDetermine required actions and instruction sizeLocate and obtain operand dataCompute result value or statusDeposit results in storage for later useDetermine successor instructionCS252/CullerLec 1.71/22/02Fast, Pipelined Instruction InterpretationInstruction RegisterOperand RegistersInstruction AddressResult RegistersNext InstructionInstruction FetchDecode &Operand FetchExecuteStore ResultsNIIFDEWNIIFDEWNIIFDEWNIIFDEWNIIFDEWTimeRegisters or MemCS252/CullerLec 1.81/22/025 Steps of MIPS DatapathFigure 3.4, Page 134 , CA:AQA 2eMemoryAccessWriteBackInstructionFetchInstr. DecodeReg. FetchExecuteAddr. CalcALUMemoryReg FileMUX MUXDataMemoryMUXSignExtendZero?IF/IDID/EXMEM/WBEX/MEM4AdderNext SEQ PCNext SEQ PCRD RD RDWB Data• Data stationary control– local decode for each instruction phase / pipeline stageNext PCAddressRS1RS2ImmMUXCS252/CullerLec 1.91/22/02Relationship of Caching and PipeliningALUMemoryReg FileMUX MUXDataMemoryMUXSignExtendZero?IF/IDID/EXMEM/WBEX/MEM4AdderNext SEQ PCNext SEQ PCRD RD RDWB Data•Next PCAddressRS1RS2ImmMUXI-CacheD-CacheCS252/CullerLec 1.101/22/02A Modern Memory Hierarchy• By taking advantage of the principle of locality:– Present the user with as much memory as is available in the cheapest technology.– Provide access at the speed offered by the fastest technology.• Requires servicing faults on the processorControlDatapathSecondaryStorage(Disk)ProcessorRegistersMainMemory(DRAM)SecondLevelCache(SRAM)On-ChipCache1s 10,000,000s (10s ms)Speed (ns): 10s 100s100sGsSize (bytes):Ks MsTertiaryStorage(Disk/Tape)10,000,000,000s (10s sec)Ts11The Other 90% of ArchitectureThe Other 90% of ArchitectureLonger PipelinesLonger PipelinesThe Prescott Pentium 4 CPU has a 31 stage pipelineThe Prescott Pentium 4 CPU has a 31 stage pipelineWider Pipelines and SpeculationWider Pipelines and SpeculationSuperscalar Superscalar ––MultiMulti--issueissueSpeculate with branch predictionSpeculate with branch predictionOut of Order ExecutionOut of Order ExecutionCaches and BuffersCaches and BuffersUp to 3 levels of caches + specialized cachesUp to 3 levels of caches + specialized cachesMemory Buffers and Reservation StationsMemory Buffers and Reservation StationsMultiple EverythingMultiple EverythingMultithreadingMultithreadingMultiprocessor System On ChipMultiprocessor System On Chip12OutlineOutlineIntroductionIntroductionProcessor ModelingProcessor ModelingSimpleScalarSimpleScalarLiberty Simulation EnvironmentLiberty Simulation EnvironmentMetropolis Processor ModelingMetropolis Processor ModelingUse of Processor Modeling in Embedded SystemsUse of Processor Modeling in Embedded SystemsConclusionsConclusions13SimpleScalarSimpleScalarOverviewOverviewThe Standard for The Standard for MicroarchitecturalMicroarchitecturalSimulationSimulationFirst Released in 1996First Released in 1996Developed by Todd Austin and Doug BurgerDeveloped by Todd Austin and Doug BurgerMultiple Levels of Models for AccuracyMultiple Levels of Models for AccuracyWritten in lowWritten in low--level highlevel high--performance sequential Cperformance sequential C--codecodeSupports a Variety of Instruction SetsSupports a Variety of Instruction SetsAlpha, ARM, PowerPC, (x86)Alpha, ARM, PowerPC, (x86)Supports a Variety of Supports a Variety of MicroarchitecturalMicroarchitecturalFeaturesFeatures14Taken From: http://www.simplescalar.com15SimpleScalarSimpleScalarToolsuiteToolsuiteTaken From: http://www.simplescalar.com16Taken From: http://www.simplescalar.com17Taken From: http://www.simplescalar.com18Taken From:
View Full Document
Unlocking...