CPU Modeling and Use for Embedded Systems Lecturer Trevor Meyerowitz EE249 Embedded Systems Design Professor Alberto Sangiovanni Vincentelli etropolis October 21st 2004 Outline Introduction Motivation Computer Architecture in 10 Minutes Flat Processor Modeling Use of Processor Modeling in Embedded Systems Conclusions 2 What is Computer Architecture Application Operating System Compiler Firmware Instr Set Proc I O system Instruction Set Architecture Datapath Control Digital Design Circuit Design Layout Coordination of many levels of abstraction Under a rapidly changing set of forces Design Measurement and Evaluation 1 22 02 CS252 Culler Lec 1 3 The Instruction Set a Critical Interface software instruction set hardware 1 22 02 CS252 Culler Lec 1 4 Levels of Representation 61C Review temp v k High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program v k v k 1 v k 1 temp lw 15 0 2 lw 16 4 2 sw 16 0 2 sw 15 4 2 0000 1010 1100 0101 1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpretation Control Signal Specification ALUOP 0 3 InstReg 9 11 MASK 1 22 02 CS252 Culler Lec 1 5 Execution Cycle Instruction Obtain instruction from program storage Fetch Instruction Determine required actions and instruction size Decode Operand Locate and obtain operand data Fetch Execute Result Compute result value or status Deposit results in storage for later use Store Next Determine successor instruction Instruction 1 22 02 CS252 Culler Lec 1 6 Fast Pipelined Instruction Interpretation Next Instruction Instruction Address Instruction Fetch Instruction Register Decode Operand Fetch Operand Registers NI NI NI NI NI IF IF IF IF IF D D D D E E E W W D E W E W W Time Execute Result Registers Store Results Registers or Mem 1 22 02 CS252 Culler Lec 1 7 5 Steps of MIPS Datapath Figure 3 4 Page 134 CA AQA 2e Execute Addr Calc Instr Decode Reg Fetch Next SEQ PC Next SEQ PC Adder 4 Zero RS1 RD RD RD MUX Sign Extend MEM WB Data Memory EX MEM ALU MUX MUX ID EX Imm Reg File IF ID Memory Address RS2 Write Back MUX Next PC Memory Access WB Data Instruction Fetch Data stationary control 1 22 02 local decode for each instruction phase pipeline stage CS252 Culler Lec 1 8 Relationship of Caching and Pipelining I Cache Next SEQ PC Next SEQ PC Adder Zero MUX RD MEM WB RD Data Memory RD EX MEM Sign Extend ALU MUX MUX ID EX Imm Reg File IF ID Memory Address RS2 WB Data RS1 D Cache 4 MUX Next PC 1 22 02 CS252 Culler Lec 1 9 A Modern Memory Hierarchy By taking advantage of the principle of locality Present the user with as much memory as is available in the cheapest technology Provide access at the speed offered by the fastest technology Requires servicing faults on the processor Processor Control Speed ns 1s Size bytes 100s 1 22 02 On Chip Cache Registers Datapath Second Level Cache SRAM Main Memory DRAM 10s 100s Ks Ms Tertiary Secondary Storage Storage Disk Tape Disk 10 000 000s 10 000 000 000s 10s sec 10s ms Ts Gs CS252 Culler Lec 1 10 The Other 90 of Architecture Longer Pipelines The Prescott Pentium 4 CPU has a 31 stage pipeline Wider Pipelines and Speculation Superscalar Multi issue Speculate with branch prediction Out of Order Execution Caches and Buffers Up to 3 levels of caches specialized caches Memory Buffers and Reservation Stations Multiple Everything Multithreading Multiprocessor System On Chip 11 Outline Introduction Processor Modeling SimpleScalar Liberty Simulation Environment Metropolis Processor Modeling Use of Processor Modeling in Embedded Systems Conclusions 12 SimpleScalar Overview The Standard for Microarchitectural Simulation First Released in 1996 Developed by Todd Austin and Doug Burger Multiple Levels of Models for Accuracy Written in low level high performance sequential C code Supports a Variety of Instruction Sets Alpha ARM PowerPC x86 Supports a Variety of Microarchitectural Features 13 Taken From http www simplescalar com 14 SimpleScalar Toolsuite Taken From http www simplescalar com 15 Taken From http www simplescalar com 16 Taken From http www simplescalar com 17 Taken From http www simplescalar com 18 Taken From http www simplescalar com 19 SimpleScalar Conclusions Solid Framework for Microarchitectural Research Used for 33 of all Computer Architecture Papers Good for examining new microarchitectural features Fast and Reliabile But Difficult to Retarget and Modify Monolithic hard to use with other tools Core Execution Semantics hard to modify Purely Sequential MOC 20 Liberty Simulation Environment A Next Generation Microarchitectural Environment From Prof David August s Princeton Research Group Compiler and Simulator Framework Advanced Language Features Structural Specification Extended Polymorphism Custom Model of Computation Composability Potential for Optimized Simulation 21 Taken From http liberty cs princeton edu 22 Taken From http liberty cs princeton edu 23 Taken From http liberty cs princeton edu 24 Taken From http liberty cs princeton edu 25 Taken From http liberty cs princeton edu 26 Taken From http liberty cs princeton edu 27 Taken From http liberty cs princeton edu 28 Liberty Conclusions This improves upon SimpleScalar in that Modular and Structural Domain Specific Language Simulator and Compiler Generation But Large learning curve Arcane entry languages Complex communication protocol Retargeting capabilities are unclear Still a monolithic environment 29 Modeling Microprocessors in Metropolis Focus on Microarchitectural Design Space Exploration in the context of a System Level Design framework Intuitive MOC and Simplified Modeling Methodology Connectivity to other tools Retargetability Outline Modeling using Kahn Process Networks ARM Processor Modeling Instruction Set Retargeting 30 Modeling with YAPI KPN Kahn Process Networks Processes communicating via unbounded FIFO s Blocking Reads Unblocking Writes Fully deterministic No notion of time YAPI Extension of KPN Non deterministic select Refinement to bounded FIFO s Our Work Characteristics Synchronous assumption Keeps FIFO lengths fixed Separation of function and timing Microarchitectural Models Single Process Model Out of Order Execution Model 2 Process ARM Models XScale Strongarm Abstract Speculative OOE Model 31 Single Process YAPI Model Add hazard detection and bubble insertion stalls Parameterize the pipeline depth Branch Predict IC Add a branch predictor Pass prediction and PC down
View Full Document
Unlocking...