DOC PREVIEW
MSU ECE 3724 - CMOS Analog Multiplexers Demultiplexers with Logic Level Conversion

This preview shows page 1-2-3-4-5-6 out of 18 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 18 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

1Data sheet acquired from Harris SemiconductorSCHS047GCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.Copyright © 2003, Texas Instruments IncorporatedCD4051B, CD4052B, CD4053BFeatures• Wide Range of Digital and Analog Signal Levels- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P• Low ON Resistance, 125Ω (Typ) Over 15VP-PSignal InputRange for VDD-VEE = 18V• High OFF Resistance, Channel Leakage of ±100pA (Typ)at VDD-VEE = 18V• Logic-Level Conversion for Digital Addressing Signals of3V to 20V (VDD-VSS = 3V to 20V) to Switch AnalogSignals to 20VP-P (VDD-VEE = 20V)• Matched Switch Characteristics, rON = 5Ω (Typ) forVDD-VEE = 15V• Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2µW (Typ) atVDD-VSS = VDD-VEE = 10V• Binary Address Decoding on Chip• 5V, 10V, and 15V Parametric Ratings• 100% Tested for Quiescent Current at 20V• Maximum Input Current of 1µA at 18V Over Full PackageTemperature Range, 100nA at 18V and 25oC• Break-Before-Make Switching Eliminates ChannelOverlapApplications• Analog and Digital Multiplexing and Demultiplexing• A/D and D/A Conversion• Signal GatingCMOS Analog Multiplexers/Demultiplexerswith Logic Level ConversionThe CD4051B, CD4052B, and CD4053B analog multiplexersare digitally-controlled analog switches having low ONimpedance and very low OFF leakage current. Control ofanalog signals up to 20VP-P can be achieved by digitalsignal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, aVDD-VEEof up to 13V can be controlled; for VDD-VEEleveldifferences above 13V, a VDD-VSS of at least 4.5V isrequired). For example, if VDD = +4.5V, VSS = 0V, andVEE= -13.5V, analog signals from -13.5V to +4.5V can becontrolled by digital inputs of 0V to 5V. These multiplexercircuits dissipate extremely low quiescent power over thefull VDD-VSS and VDD-VEE supply-voltage ranges,independent of the logic state of the control signals. Whena logic “1” is present at the inhibit input terminal, allchannels are off.The CD4051B is a single 8-Channel multiplexer having threebinary control inputs, A, B, and C, and an inhibit input. Thethree binary signals select 1 of 8 channels to be turned on,and connect one of the 8 inputs to the output.The CD4052B is a differential 4-Channel multiplexer havingtwo binary control inputs, A and B, and an inhibit input. Thetwo binary input signals select 1 of 4 pairs of channels to beturned on and connect the analog inputs to the outputs.The CD4053B is a triple 2-Channel multiplexer having threeseparate digital control inputs, A, B, and C, and an inhibitinput. Each control input selects one of a pair of channelswhich are connected in a single-pole, double-throwconfiguration.When these devices are used as demultiplexers, the“CHANNEL IN/OUT” terminals are the outputs and the“COMMON OUT/IN” terminals are the inputs.NOTE: When ordering, use the entire part number. The suffixes 96and R denote tape and reel. The suffix T denotes a small-quantityreel of 250.Ordering InformationPART NUMBERTEMP. RANGE(oC) PACKAGECD4051BF3A, CD4052BF3A,CD4053BF3A-55 to 125 16 Ld CERAMICDIPCD4051BE, CD4052BE,CD4053BE-55 to 125 16 Ld PDIPCD4051BM, CD4051BMT,CD4051BM96CD4052BM, CD4052BMT,CD4052BM96CD4053BM, CD4053BMT,CD4053BM96-55 to 125 16 Ld SOICCD4051BNSR, CD4052BNSR,CD4053BNSR-55 to 125 16 Ld SOPCD4051BPW, CD4051BPWR,CD4052BPW, CD4052BPWRCD4053BPW, CD4053BPWR-55 to 125 16 Ld TSSOPAugust 1998 - Revised October 2003[ /Title(CD4051B,CD4052B,CD4053B)/Sub-ject(CMOSAnalogMulti-plex-ers/Demultiplex-ers withLogicLevelConver-sion)/Author()/Key-words(HarrisSemi-conduc-tor,CD40002PinoutsCD4051B (PDIP, CDIP, SOIC, SOP, TSSOP)TOP VIEWCD4052B (PDIP, CDIP, SOP, TSSOP)TOP VIEWCD4053B (PDIP, CDIP, SOP, TSSOP)TOP VIEW1415169131211101234576846COM OUT/IN75INHVSSVEEVDD103ABC2CHANNELS IN/OUTCHANNELSIN/OUTCHANNELSIN/OUT1415169131211101234576802COMMON “Y” OUT/IN31INHVSSVEEVDD1COMMON “X” OUT/IN03AB2Y CHANNELSIN/OUTY CHANNELSIN/OUTX CHANNELSIN/OUTX CHANNELSIN/OUT14151691312111012345768bybxcyOUT/IN CX OR CYIN/OUT CXINHVSSVEEVDDOUT/IN ax OR ayayaxABCOUT/IN bx OR byIN/OUTIN/OUTFunctional Block DiagramsCD4051B111096A †B †C †INH †134 2 5 1 12 15 14TGTGTGTGTGTGTGTG3COMMONOUT/IN01234567BINARYTO1 OF 8DECODERWITHINHIBITLOGICLEVELCONVERSION8 7VSSVEE16VDDCHANNEL IN/OUT†All inputs are protected by standard CMOS protection network.CD4051B, CD4052B, CD4053B3CD4052BCD4053BFunctional Block Diagrams (Continued)1211 15 1401233210X CHANNELS IN/OUTY CHANNELS IN/OUTBINARYTO1 OF 4DECODERWITHINHIBIT133COMMON YOUT/INCOMMON XOUT/IN78166910A †B †INH †VSSVEEVDDTGTGTGTGTGTGTGTG4251LOGICLEVELCONVERSION111096A †B †C †INH †123 5 1 2 13TGTGTGTGTGTG4COMMONOUT/INaxaybxbycxcy87VSSVEE16VDDIN/OUT1514BINARY TO1 OF 2DECODERSWITHINHIBITLOGICLEVELCONVERSIONVDD†All inputs are protected by standard CMOS protection network.COMMONOUT/INCOMMONOUT/INax OR aybx OR bycx OR cyCD4051B, CD4052B, CD4053B4TRUTH TABLESINPUT STATES“ON” CHANNEL(S)INHIBIT C B ACD4051B0000 00001 10010 20011 30100 40101 50110 60111 71 X X X NoneCD4052BINHIBIT B A0 0 0 0x, 0y0 0 1 1x, 1y0 1 0 2x, 2y0 1 1 3x, 3y1 X X NoneCD4053BINHIBIT A OR B OR C0 0 ax or bx or cx0 1 ay or by or cy1 X NoneX = Don’t CareCD4051B, CD4052B, CD4053B5Absolute Maximum RatingsThermal InformationSupply Voltage (V+ to V-)Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20VDC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5VDC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mAOperating ConditionsTemperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oCPackage Thermal Impedance, θJA(see Note 1):E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/WM (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/WNS (SOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/WPW (TSSOP) package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/WMaximum Junction Temperature (Ceramic Package) . . . . . . . . .175oCMaximum Junction Temperature (Plastic Package) . . . . . . . .150oCMaximum Storage Temperature Range. . . . . . . . . . -65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC(SOIC - Lead Tips Only)CAUTION: Stresses above


View Full Document

MSU ECE 3724 - CMOS Analog Multiplexers Demultiplexers with Logic Level Conversion

Documents in this Course
Timers

Timers

38 pages

TEST 4

TEST 4

9 pages

Flags

Flags

6 pages

Timers

Timers

6 pages

Timers

Timers

54 pages

TEST2

TEST2

8 pages

Load more
Download CMOS Analog Multiplexers Demultiplexers with Logic Level Conversion
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view CMOS Analog Multiplexers Demultiplexers with Logic Level Conversion and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view CMOS Analog Multiplexers Demultiplexers with Logic Level Conversion 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?